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      1 /*
      2  * Copyright (C) 2008 The Android Open Source Project
      3  * All rights reserved.
      4  *
      5  * Redistribution and use in source and binary forms, with or without
      6  * modification, are permitted provided that the following conditions
      7  * are met:
      8  *  * Redistributions of source code must retain the above copyright
      9  *    notice, this list of conditions and the following disclaimer.
     10  *  * Redistributions in binary form must reproduce the above copyright
     11  *    notice, this list of conditions and the following disclaimer in
     12  *    the documentation and/or other materials provided with the
     13  *    distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     16  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     17  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
     18  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
     19  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
     22  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
     25  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 #ifndef _ARM_MACHINE_CPU_FEATURES_H
     29 #define _ARM_MACHINE_CPU_FEATURES_H
     30 
     31 /* The purpose of this file is to define several macros corresponding
     32  * to CPU features that may or may not be available at build time on
     33  * on the target CPU.
     34  *
     35  * This is done to abstract us from the various ARM Architecture
     36  * quirks and alphabet soup.
     37  *
     38  * IMPORTANT: We have no intention to support anything below an ARMv4T !
     39  */
     40 
     41 /* __ARM_ARCH__ is a number corresponding to the ARM revision
     42  * we're going to support
     43  *
     44  * it looks like our toolchain doesn't define __ARM_ARCH__
     45  * so try to guess it.
     46  *
     47  *
     48  *
     49  */
     50 #ifndef __ARM_ARCH__
     51 
     52 #  if defined __ARM_ARCH_7__   || defined __ARM_ARCH_7A__ || \
     53       defined __ARM_ARCH_7R__  || defined __ARM_ARCH_7M__
     54 
     55 #    define __ARM_ARCH__ 7
     56 
     57 #  elif defined __ARM_ARCH_6__   || defined __ARM_ARCH_6J__ || \
     58       defined __ARM_ARCH_6K__  || defined __ARM_ARCH_6Z__ || \
     59       defined __ARM_ARCH_6KZ__ || defined __ARM_ARCH_6T2__
     60 #
     61 #    define __ARM_ARCH__ 6
     62 #
     63 #  elif defined __ARM_ARCH_5__ || defined __ARM_ARCH_5T__ || \
     64         defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__
     65 #
     66 #    define __ARM_ARCH__ 5
     67 #
     68 #  elif defined __ARM_ARCH_4T__
     69 #
     70 #    define __ARM_ARCH__ 4
     71 #
     72 #  elif defined __ARM_ARCH_4__
     73 #    error ARMv4 is not supported, please use ARMv4T at a minimum
     74 #  else
     75 #    error Unknown or unsupported ARM architecture
     76 #  endif
     77 #endif
     78 
     79 /* experimental feature used to check that our ARMv4 workarounds
     80  * work correctly without a real ARMv4 machine */
     81 #ifdef BIONIC_EXPERIMENTAL_FORCE_ARMV4
     82 #  undef  __ARM_ARCH__
     83 #  define __ARM_ARCH__  4
     84 #endif
     85 
     86 /* define __ARM_HAVE_5TE if we have the ARMv5TE instructions */
     87 #if __ARM_ARCH__ > 5
     88 #  define  __ARM_HAVE_5TE  1
     89 #elif __ARM_ARCH__ == 5
     90 #  if defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__
     91 #    define __ARM_HAVE_5TE  1
     92 #  endif
     93 #endif
     94 
     95 /* instructions introduced in ARMv5 */
     96 #if __ARM_ARCH__ >= 5
     97 #  define  __ARM_HAVE_BLX  1
     98 #  define  __ARM_HAVE_CLZ  1
     99 #  define  __ARM_HAVE_LDC2 1
    100 #  define  __ARM_HAVE_MCR2 1
    101 #  define  __ARM_HAVE_MRC2 1
    102 #  define  __ARM_HAVE_STC2 1
    103 #endif
    104 
    105 /* ARMv5TE introduces a few instructions */
    106 #if __ARM_HAVE_5TE
    107 #  define  __ARM_HAVE_PLD   1
    108 #  define  __ARM_HAVE_MCRR  1
    109 #  define  __ARM_HAVE_MRRC  1
    110 #endif
    111 
    112 /* define __ARM_HAVE_HALFWORD_MULTIPLY when half-word multiply instructions
    113  * this means variants of: smul, smulw, smla, smlaw, smlal
    114  */
    115 #if __ARM_HAVE_5TE
    116 #  define  __ARM_HAVE_HALFWORD_MULTIPLY  1
    117 #endif
    118 
    119 /* define __ARM_HAVE_PAIR_LOAD_STORE when 64-bit memory loads and stored
    120  * into/from a pair of 32-bit registers is supported throuhg 'ldrd' and 'strd'
    121  */
    122 #if __ARM_HAVE_5TE
    123 #  define  __ARM_HAVE_PAIR_LOAD_STORE 1
    124 #endif
    125 
    126 /* define __ARM_HAVE_SATURATED_ARITHMETIC is you have the saturated integer
    127  * arithmetic instructions: qdd, qdadd, qsub, qdsub
    128  */
    129 #if __ARM_HAVE_5TE
    130 #  define  __ARM_HAVE_SATURATED_ARITHMETIC 1
    131 #endif
    132 
    133 /* define __ARM_HAVE_PC_INTERWORK when a direct assignment to the
    134  * pc register will switch into thumb/ARM mode depending on bit 0
    135  * of the new instruction address. Before ARMv5, this was not the
    136  * case, and you have to write:
    137  *
    138  *     mov  r0, [<some address>]
    139  *     bx   r0
    140  *
    141  * instead of:
    142  *
    143  *     ldr  pc, [<some address>]
    144  *
    145  * note that this affects any instruction that explicitly changes the
    146  * value of the pc register, including ldm { ...,pc } or 'add pc, #offset'
    147  */
    148 #if __ARM_ARCH__ >= 5
    149 #  define __ARM_HAVE_PC_INTERWORK
    150 #endif
    151 
    152 /* define __ARM_HAVE_LDREX_STREX for ARMv6 and ARMv7 architecture to be
    153  * used in replacement of deprecated swp instruction
    154  */
    155 #if __ARM_ARCH__ >= 6
    156 #  define __ARM_HAVE_LDREX_STREX
    157 #endif
    158 
    159 /* define __ARM_HAVE_DMB for ARMv7 architecture
    160  */
    161 #if __ARM_ARCH__ >= 7
    162 #  define __ARM_HAVE_DMB
    163 #endif
    164 
    165 /* define __ARM_HAVE_LDREXD for ARMv7 architecture
    166  * (also present in ARMv6K, but not implemented in ARMv7-M, neither of which
    167  * we care about)
    168  */
    169 #if __ARM_ARCH__ >= 7
    170 #  define __ARM_HAVE_LDREXD
    171 #endif
    172 
    173 /* define _ARM_HAVE_VFP if we have VFPv3
    174  */
    175 #if __ARM_ARCH__ >= 7 && defined __VFP_FP__
    176 #  define __ARM_HAVE_VFP
    177 #endif
    178 
    179 /* define _ARM_HAVE_NEON for ARMv7 architecture if we support the
    180  * Neon SIMD instruction set extensions. This also implies
    181  * that VFPv3-D32 is supported.
    182  */
    183 #if __ARM_ARCH__ >= 7 && defined __ARM_NEON__
    184 #  define __ARM_HAVE_NEON
    185 #endif
    186 
    187 /* Assembly-only macros */
    188 #ifdef __ASSEMBLY__
    189 
    190 /* define a handy PLD(address) macro since the cache preload
    191  * is an optional opcode
    192  */
    193 #if __ARM_HAVE_PLD
    194 #  define  PLD(reg,offset)    pld    [reg, offset]
    195 #else
    196 #  define  PLD(reg,offset)    /* nothing */
    197 #endif
    198 
    199 #endif /* ! __ASSEMBLY__ */
    200 
    201 #endif /* _ARM_MACHINE_CPU_FEATURES_H */
    202