1 ; RUN: opt < %s -instcombine -S | FileCheck %s 2 3 ; CHECK: @sdiv1 4 ; CHECK: sdiv i32 %x, 8 5 define i32 @sdiv1(i32 %x) { 6 %y = sdiv i32 %x, 8 7 ret i32 %y 8 } 9 10 ; CHECK: @sdiv2 11 ; CHECK: ashr exact i32 %x, 3 12 define i32 @sdiv2(i32 %x) { 13 %y = sdiv exact i32 %x, 8 14 ret i32 %y 15 } 16 17 ; CHECK: @sdiv3 18 ; CHECK: %y = srem i32 %x, 3 19 ; CHECK: %z = sub i32 %x, %y 20 ; CHECK: ret i32 %z 21 define i32 @sdiv3(i32 %x) { 22 %y = sdiv i32 %x, 3 23 %z = mul i32 %y, 3 24 ret i32 %z 25 } 26 27 ; CHECK: @sdiv4 28 ; CHECK: ret i32 %x 29 define i32 @sdiv4(i32 %x) { 30 %y = sdiv exact i32 %x, 3 31 %z = mul i32 %y, 3 32 ret i32 %z 33 } 34 35 ; CHECK: i32 @sdiv5 36 ; CHECK: %y = srem i32 %x, 3 37 ; CHECK: %z = sub i32 %y, %x 38 ; CHECK: ret i32 %z 39 define i32 @sdiv5(i32 %x) { 40 %y = sdiv i32 %x, 3 41 %z = mul i32 %y, -3 42 ret i32 %z 43 } 44 45 ; CHECK: @sdiv6 46 ; CHECK: %z = sub i32 0, %x 47 ; CHECK: ret i32 %z 48 define i32 @sdiv6(i32 %x) { 49 %y = sdiv exact i32 %x, 3 50 %z = mul i32 %y, -3 51 ret i32 %z 52 } 53 54 ; CHECK: @udiv1 55 ; CHECK: ret i32 %x 56 define i32 @udiv1(i32 %x, i32 %w) { 57 %y = udiv exact i32 %x, %w 58 %z = mul i32 %y, %w 59 ret i32 %z 60 } 61 62 ; CHECK: @udiv2 63 ; CHECK: %z = lshr exact i32 %x, %w 64 ; CHECK: ret i32 %z 65 define i32 @udiv2(i32 %x, i32 %w) { 66 %y = shl i32 1, %w 67 %z = udiv exact i32 %x, %y 68 ret i32 %z 69 } 70 71 ; CHECK: @ashr1 72 ; CHECK: %B = ashr exact i64 %A, 2 73 ; CHECK: ret i64 %B 74 define i64 @ashr1(i64 %X) nounwind { 75 %A = shl i64 %X, 8 76 %B = ashr i64 %A, 2 ; X/4 77 ret i64 %B 78 } 79 80 ; PR9120 81 ; CHECK: @ashr_icmp1 82 ; CHECK: %B = icmp eq i64 %X, 0 83 ; CHECK: ret i1 %B 84 define i1 @ashr_icmp1(i64 %X) nounwind { 85 %A = ashr exact i64 %X, 2 ; X/4 86 %B = icmp eq i64 %A, 0 87 ret i1 %B 88 } 89 90 ; CHECK: @ashr_icmp2 91 ; CHECK: %Z = icmp slt i64 %X, 16 92 ; CHECK: ret i1 %Z 93 define i1 @ashr_icmp2(i64 %X) nounwind { 94 %Y = ashr exact i64 %X, 2 ; x / 4 95 %Z = icmp slt i64 %Y, 4 ; x < 16 96 ret i1 %Z 97 } 98 99 ; PR9998 100 ; Make sure we don't transform the ashr here into an sdiv 101 ; CHECK: @pr9998 102 ; CHECK: = and i32 %V, 1 103 ; CHECK: %Z = icmp ne 104 ; CHECK: ret i1 %Z 105 define i1 @pr9998(i32 %V) nounwind { 106 entry: 107 %W = shl i32 %V, 31 108 %X = ashr exact i32 %W, 31 109 %Y = sext i32 %X to i64 110 %Z = icmp ugt i64 %Y, 7297771788697658747 111 ret i1 %Z 112 } 113 114 115 ; CHECK: @udiv_icmp1 116 ; CHECK: icmp ne i64 %X, 0 117 define i1 @udiv_icmp1(i64 %X) nounwind { 118 %A = udiv exact i64 %X, 5 ; X/5 119 %B = icmp ne i64 %A, 0 120 ret i1 %B 121 } 122 123 ; CHECK: @sdiv_icmp1 124 ; CHECK: icmp eq i64 %X, 0 125 define i1 @sdiv_icmp1(i64 %X) nounwind { 126 %A = sdiv exact i64 %X, 5 ; X/5 == 0 --> x == 0 127 %B = icmp eq i64 %A, 0 128 ret i1 %B 129 } 130 131 ; CHECK: @sdiv_icmp2 132 ; CHECK: icmp eq i64 %X, 5 133 define i1 @sdiv_icmp2(i64 %X) nounwind { 134 %A = sdiv exact i64 %X, 5 ; X/5 == 1 --> x == 5 135 %B = icmp eq i64 %A, 1 136 ret i1 %B 137 } 138 139 ; CHECK: @sdiv_icmp3 140 ; CHECK: icmp eq i64 %X, -5 141 define i1 @sdiv_icmp3(i64 %X) nounwind { 142 %A = sdiv exact i64 %X, 5 ; X/5 == -1 --> x == -5 143 %B = icmp eq i64 %A, -1 144 ret i1 %B 145 } 146 147 ; CHECK: @sdiv_icmp4 148 ; CHECK: icmp eq i64 %X, 0 149 define i1 @sdiv_icmp4(i64 %X) nounwind { 150 %A = sdiv exact i64 %X, -5 ; X/-5 == 0 --> x == 0 151 %B = icmp eq i64 %A, 0 152 ret i1 %B 153 } 154 155 ; CHECK: @sdiv_icmp5 156 ; CHECK: icmp eq i64 %X, -5 157 define i1 @sdiv_icmp5(i64 %X) nounwind { 158 %A = sdiv exact i64 %X, -5 ; X/-5 == 1 --> x == -5 159 %B = icmp eq i64 %A, 1 160 ret i1 %B 161 } 162 163 ; CHECK: @sdiv_icmp6 164 ; CHECK: icmp eq i64 %X, 5 165 define i1 @sdiv_icmp6(i64 %X) nounwind { 166 %A = sdiv exact i64 %X, -5 ; X/-5 == 1 --> x == 5 167 %B = icmp eq i64 %A, -1 168 ret i1 %B 169 } 170 171
