| /external/v8/src/ia32/ |
| cpu-ia32.cc | 28 // CPU specific code for ia32 independent of OS goes here.
38 #include "cpu.h"
44 void CPU::SetUp() {
49 bool CPU::SupportsCrankshaft() {
54 void CPU::FlushICache(void* start, size_t size) {
58 // is patched on an intel CPU the core performing the patching will have its
76 void CPU::DebugBreak() {
|
| /external/v8/src/x64/ |
| cpu-x64.cc | 28 // CPU specific code for x64 independent of OS goes here.
38 #include "cpu.h"
44 void CPU::SetUp() {
49 bool CPU::SupportsCrankshaft() {
54 void CPU::FlushICache(void* start, size_t size) {
58 // is patched on an intel CPU the core performing the patching will have its
76 void CPU::DebugBreak() {
|
| /external/llvm/lib/Target/XCore/ |
| XCoreSubtarget.cpp | 27 const std::string &CPU, const std::string &FS)
28 : XCoreGenSubtargetInfo(TT, CPU, FS)
|
| XCoreSubtarget.h | 34 XCoreSubtarget(const std::string &TT, const std::string &CPU,
39 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
| XCoreTargetMachine.cpp | 24 StringRef CPU, StringRef FS,
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
29 Subtarget(TT, CPU, FS),
|
| /external/llvm/lib/Target/Sparc/ |
| SparcSubtarget.cpp | 26 SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU,
28 SparcGenSubtargetInfo(TT, CPU, FS),
35 std::string CPUName = CPU;
|
| SparcTargetMachine.cpp | 29 StringRef CPU, StringRef FS,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 Subtarget(TT, CPU, FS, is64bit),
78 StringRef TT, StringRef CPU,
84 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
90 StringRef TT, StringRef CPU,
96 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
|
| SparcSubtarget.h | 34 SparcSubtarget(const std::string &TT, const std::string &CPU,
43 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
| /external/v8/src/ |
| cpu.h | 45 // CPU
53 class CPU : public AllStatic {
55 // Initializes the cpu architecture support. Called once at VM startup.
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430Subtarget.cpp | 27 const std::string &CPU,
29 MSP430GenSubtargetInfo(TT, CPU, FS) {
|
| MSP430Subtarget.h | 33 MSP430Subtarget(const std::string &TT, const std::string &CPU,
38 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
| MSP430TargetMachine.cpp | 29 StringRef CPU,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 Subtarget(TT, CPU, FS),
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSubtarget.cpp | 34 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS):
35 HexagonGenSubtargetInfo(TT, CPU, FS),
37 CPUString(CPU.str()) {
38 ParseSubtargetFeatures(CPU, FS);
52 // Initialize scheduling itinerary for the specified CPU.
|
| /external/v8/src/arm/ |
| cpu-arm.cc | 28 // CPU specific code for arm independent of OS goes here.
37 #include "cpu.h"
44 void CPU::SetUp() {
49 bool CPU::SupportsCrankshaft() {
54 void CPU::FlushICache(void* start, size_t size) {
110 void CPU::DebugBreak() {
|
| /external/v8/src/mips/ |
| cpu-mips.cc | 28 // CPU specific code for arm independent of OS goes here.
41 #include "cpu.h"
50 void CPU::SetUp() {
55 bool CPU::SupportsCrankshaft() {
60 void CPU::FlushICache(void* start, size_t size) {
91 void CPU::DebugBreak() {
|
| /external/llvm/lib/MC/ |
| MCSubtargetInfo.cpp | 21 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
40 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
45 /// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
47 uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) {
49 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
72 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
84 KV.Key = CPU.data();
87 if (Found == ProcItins+NumProcs || StringRef(Found->Key) != CPU) {
88 errs() << "'" << CPU
|
| /external/qemu/distrib/ |
| update-audio.sh | 27 CPU=`uname -p`
28 if [ "$CPU" == "i386" ] ; then
35 CPU=`uname -m`
36 case "$CPU" in
38 CPU=x86
41 OS=linux-$CPU
|
| /external/llvm/include/llvm/MC/ |
| MCSubtargetInfo.h | 39 uint64_t FeatureBits; // Feature bits for current CPU + FS
42 void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
60 /// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
62 uint64_t ReInitMCSubtargetInfo(StringRef CPU, StringRef FS);
72 /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
74 InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeSubtarget.cpp | 27 const std::string &CPU,
29 MBlazeGenSubtargetInfo(TT, CPU, FS),
34 std::string CPUName = CPU;
39 // Only use instruction scheduling if the selected CPU has an instruction
40 // itinerary (the default CPU is the only one that doesn't).
42 DEBUG(dbgs() << "CPU " << CPUName << "(" << HasItin << ")\n");
44 // Initialize scheduling itinerary for the specified CPU.
|
| /external/llvm/lib/Target/PTX/ |
| PTXSubtarget.cpp | 27 PTXSubtarget::PTXSubtarget(const std::string &TT, const std::string &CPU,
29 : PTXGenSubtargetInfo(TT, CPU, FS),
35 std::string TARGET = CPU;
|
| /external/chromium/base/ |
| cpu.h | 16 class BASE_API CPU {
19 CPU();
21 // Accessors for CPU information.
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUSubtarget.h | 56 SPUSubtarget(const std::string &TT, const std::string &CPU,
61 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
| /external/llvm/lib/Target/CppBackend/ |
| CPPTargetMachine.h | 26 StringRef CPU, StringRef FS, const TargetOptions &Options,
29 : TargetMachine(T, TT, CPU, FS, Options) {}
|
| /external/llvm/lib/Target/Mips/ |
| MipsTargetMachine.cpp | 38 StringRef CPU, StringRef FS, const TargetOptions &Options,
42 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
43 Subtarget(TT, CPU, FS, isLittle),
60 StringRef CPU, StringRef FS, const TargetOptions &Options,
63 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
69 StringRef CPU, StringRef FS, const TargetOptions &Options,
72 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
78 StringRef CPU, StringRef FS, const TargetOptions &Options,
81 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
87 StringRef CPU, StringRef FS, const TargetOptions &Options
[all...] |
| /external/clang/include/clang/Basic/ |
| TargetOptions.h | 25 /// If given, the name of the target CPU to generate code for.
26 std::string CPU;
|
