| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
14 #include "Hexagon.h"
34 /// Constants for Hexagon instructions.
58 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
73 case Hexagon::LDriw:
74 case Hexagon::LDrid:
75 case Hexagon::LDrih:
76 case Hexagon::LDrib
[all...] |
| HexagonRegisterInfo.cpp | 1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
16 #include "Hexagon.h"
42 : HexagonGenRegisterInfo(Hexagon::R31),
51 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
54 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19
[all...] |
| HexagonVarargsCallingConvention.h | 53 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
54 Hexagon::R5
66 Hexagon::D0, Hexagon::D1, Hexagon::D2
109 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4
[all...] |
| HexagonExpandPredSpillCode.cpp | 9 // The Hexagon processor has no instructions that load or store predicate
55 return "Hexagon Expand Predicate Spill Code";
77 if (Opc == Hexagon::STriw_pred) {
85 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
87 if (!TII->isValidOffset(Hexagon::STriw, Offset)) {
88 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
90 TII->get(Hexagon::CONST32_Int_Real),
92 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
95 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
98 TII->get(Hexagon::STriw)
[all...] |
| HexagonCFGOptimizer.cpp | 45 return "Hexagon CFG Optimizer";
54 return (Opc == Hexagon::JMP_c) || (Opc == Hexagon::JMP_cNot)
55 || (Opc == Hexagon::JMP_cdnPt) || (Opc == Hexagon::JMP_cdnNotPt);
60 return (Opc == Hexagon::JMP);
70 case Hexagon::JMP_c:
71 NewOpcode = Hexagon::JMP_cNot;
74 case Hexagon::JMP_cNot:
75 NewOpcode = Hexagon::JMP_c
[all...] |
| HexagonMachineFunctionInfo.h | 1 //=- HexagonMachineFuctionInfo.h - Hexagon machine function info --*- C++ -*-=//
17 namespace Hexagon {
23 /// Hexagon target-specific information for each MachineFunction.
56 PacketInfo[MI] |= Hexagon::StartPacket;
59 PacketInfo[MI] |= Hexagon::EndPacket;
63 (PacketInfo.find(MI)->second & Hexagon::StartPacket));
67 (PacketInfo.find(MI)->second & Hexagon::EndPacket));
|
| HexagonPeephole.cpp | 1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
38 #define DEBUG_TYPE "hexagon-peephole"
39 #include "Hexagon.h"
60 static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole",
68 static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp",
72 static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
89 return "Hexagon optimize redundant zero and size extends";
127 if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) {
145 (MI->getOpcode() == Hexagon::NOT_p)) {
169 if (Src.getSubReg() != Hexagon::subreg_loreg
[all...] |
| Makefile | 1 ##===- lib/Target/Hexagon/Makefile -------------------------*- Makefile -*-===##
11 TARGET = Hexagon
|
| HexagonSplitTFRCondSets.cpp | 63 return "Hexagon Split TFRCondSets";
85 if (Opc == Hexagon::TFR_condset_rr) {
94 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_cPt),
98 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_cNotPt),
103 } else if (Opc == Hexagon::TFR_condset_ii) {
108 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFRI_cPt),
110 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFRI_cNotPt),
|
| HexagonRegisterInfo.h | 1 //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
36 #define HEXAGON_RESERVED_REG_1 Hexagon::R10
37 #define HEXAGON_RESERVED_REG_2 Hexagon::R11
|
| HexagonISelDAGToDAG.cpp | 1 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
10 // This file defines an instruction selector for the Hexagon target.
14 #define DEBUG_TYPE "hexagon-isel"
30 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
35 /// Subtarget - Keep a pointer to the Hexagon Subtarget around so that we can
67 return "Hexagon DAG->DAG Pattern Instruction Selection";
103 /// Hexagon-specific DAG, ready for instruction scheduling.
233 return Hexagon::TFR_RsPd;
235 return Hexagon::AND_pp
[all...] |
| HexagonHardwareLoops.cpp | 10 // This pass identifies loops where we can generate the Hexagon hardware
30 #include "Hexagon.h"
67 const char *getPassName() const { return "Hexagon Hardware Loops"; }
171 const char *getPassName() const { return "Hexagon Hardware Loop Fixup"; }
204 return MI->getOpcode() == Hexagon::LOOP0_r ||
205 MI->getOpcode() == Hexagon::LOOP0_i;
211 return MI->getOpcode() == Hexagon::CMPEQri;
223 DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n");
352 if (DefInstr && DefInstr->getOpcode() == Hexagon::TFRI) {
373 Hexagon::ADD_ri && MI->getOperand(1).getReg() == IVReg)
[all...] |
| HexagonFrameLowering.cpp | 12 #include "Hexagon.h"
40 "disable-hexagon-dealloc-ret",
42 cl::desc("Disable Dealloc Return for Hexagon target"));
108 assert((MI->getOpcode() == Hexagon::ADJDYNALLOC) &&
149 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
152 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real),
154 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::SUB_rr),
159 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
169 return RetOpcode == Hexagon::TCRETURNtg || RetOpcode == Hexagon::TCRETURNtext;
[all...] |
| HexagonISelLowering.cpp | 1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
43 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,
44 cl::desc("Control jump table emission on Hexagon target"));
48 // Implement calling convention for Hexagon.
162 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4
[all...] |
| HexagonCallingConvLower.cpp | 17 #include "Hexagon.h"
101 // For Hexagon, Return small structures in registers.
104 unsigned Reg = Hexagon::R0;
110 unsigned Reg = Hexagon::D0;
|
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCTargetDesc.cpp | 1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
10 // This file provides Hexagon specific target descriptions.
43 InitHexagonMCRegisterInfo(X, Hexagon::R0);
60 MachineLocation Src(Hexagon::R30, 0);
|
| /external/clang/include/clang/Basic/ |
| TargetBuiltins.h | 99 /// Hexagon builtins
100 namespace Hexagon {
|
| /external/llvm/lib/Target/Hexagon/InstPrinter/ |
| HexagonInstPrinter.cpp | 1 //===- HexagonInstPrinter.cpp - Convert Hexagon MCInst to assembly syntax -===//
10 // This class prints an Hexagon MCInst to a .s file.
15 #include "Hexagon.h"
44 if (MI->getOpcode() == Hexagon::ENDLOOP0) {
48 Nop.setOpcode(Hexagon::NOP);
|
| /external/clang/lib/Basic/ |
| Targets.cpp | [all...] |
| /external/llvm/ |
| configure | [all...] |
| /external/llvm/projects/sample/ |
| configure | [all...] |
