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  /external/llvm/lib/Target/ARM/
ARMExpandPseudoInsts.cpp 89 // For quad-register load-lane and store-lane pseudo instructors, the
91 // OddDblSpc depending on the lane number operand.
108 unsigned char RegElts; // elements per D register; used for lane ops
502 // The lane operand is always the 3rd from last operand, before the 2
504 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
506 // Adjust the lane and spacing as needed for Q registers.
507 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
508 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
510 Lane -= RegElts
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ARMCodeEmitter.cpp     [all...]
ARMISelLowering.cpp     [all...]
ARMISelDAGToDAG.cpp 224 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
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  /external/jpeg/
jmemdosa.asm 4 ; Copyright (C) 1992, Thomas G. Lane.
  /external/qemu/distrib/jpeg-6b/
jmemdosa.asm 4 ; Copyright (C) 1992, Thomas G. Lane.

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