| /external/llvm/lib/VMCore/ |
| ValueTypes.cpp | 103 case MVT::i1: return "i1";
104 case MVT::i8: return "i8";
105 case MVT::i16: return "i16";
106 case MVT::i32: return "i32";
107 case MVT::i64: return "i64";
108 case MVT::i128: return "i128";
109 case MVT::f16: return "f16";
110 case MVT::f32: return "f32";
111 case MVT::f64: return "f64";
112 case MVT::f80: return "f80"
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 30 /// MVT - Machine Value Type. Every type that is supported natively by some
32 /// type can be represented by a MVT.
33 class MVT {
101 // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
142 MVT() : SimpleTy((SimpleValueType)(INVALID_SIMPLE_VALUE_TYPE)) {}
143 MVT(SimpleValueType SVT) : SimpleTy(SVT) { }
145 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
146 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
147 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
148 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy;
[all...] |
| FastISel.h | 160 virtual unsigned FastEmit_(MVT VT,
161 MVT RetVT,
168 virtual unsigned FastEmit_r(MVT VT,
169 MVT RetVT,
177 virtual unsigned FastEmit_rr(MVT VT,
178 MVT RetVT,
187 virtual unsigned FastEmit_ri(MVT VT,
188 MVT RetVT,
197 virtual unsigned FastEmit_rf(MVT VT,
198 MVT RetVT
[all...] |
| CallingConvLower.h | 61 MVT ValVT;
64 MVT LocVT;
67 static CCValAssign getReg(unsigned ValNo, MVT ValVT,
68 unsigned RegNo, MVT LocVT,
81 static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
82 unsigned RegNo, MVT LocVT,
90 static CCValAssign getMem(unsigned ValNo, MVT ValVT,
91 unsigned Offset, MVT LocVT,
104 static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
105 unsigned Offset, MVT LocVT
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 41 if (VT==MVT::i1) retval=3;
42 if (VT==MVT::i8) retval=3;
43 if (VT==MVT::i16) retval=2;
103 addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
104 addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
105 addRegisterClass(MVT::i32, SPU::R32CRegisterClass);
106 addRegisterClass(MVT::i64, SPU::R64CRegisterClass);
107 addRegisterClass(MVT::f32, SPU::R32FPRegisterClass);
108 addRegisterClass(MVT::f64, SPU::R64FPRegisterClass);
109 addRegisterClass(MVT::i128, SPU::GPRCRegisterClass)
2746 MVT mvt = Op0VT == MVT::i64 ? MVT::v2i64 : MVT::v4i32; local
[all...] |
| SPUISelDAGToDAG.cpp | 82 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
84 } else if (vt == MVT::i32) {
100 if (vt == MVT::f32) {
116 ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
117 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
118 ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
119 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
121 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
131 ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32))
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 50 CC_Hexagon(unsigned ValNo, MVT ValVT,
51 MVT LocVT, CCValAssign::LocInfo LocInfo,
55 CC_Hexagon32(unsigned ValNo, MVT ValVT,
56 MVT LocVT, CCValAssign::LocInfo LocInfo,
60 CC_Hexagon64(unsigned ValNo, MVT ValVT,
61 MVT LocVT, CCValAssign::LocInfo LocInfo,
65 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
66 MVT LocVT, CCValAssign::LocInfo LocInfo,
70 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
71 MVT LocVT, CCValAssign::LocInfo LocInfo
[all...] |
| HexagonISelDAGToDAG.cpp | 276 if (MemType == MVT::i64 && isShiftedInt<11,3>(Offset)) {
279 if (MemType == MVT::i32 && isShiftedInt<11,2>(Offset)) {
282 if (MemType == MVT::i16 && isShiftedInt<11,1>(Offset)) {
285 if (MemType == MVT::i8 && isInt<11>(Offset)) {
308 MVT PointerTy = TLI.getPointerTy();
317 if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed;
318 else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed;
319 else if (LoadedVT == MVT::i16) Opcode = Hexagon::LDrih_indexed;
320 else if (LoadedVT == MVT::i8) Opcode = Hexagon::LDrib_indexed;
327 MVT::Other
[all...] |
| HexagonVarargsCallingConvention.h | 39 (MVT(MVT::i64).getSizeInBits() / 8))) {
48 if (LocVT == MVT::i32 ||
49 LocVT == MVT::i16 ||
50 LocVT == MVT::i8 ||
51 LocVT == MVT::f32) {
63 if (LocVT == MVT::i64 ||
64 LocVT == MVT::f64) {
106 if (LocVT == MVT::i32 ||
107 LocVT == MVT::f32)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 28 static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
58 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
64 if (LocVT == MVT::v2f64 &&
71 static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
106 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
112 if (LocVT == MVT::v2f64 &
[all...] |
| ARMSelectionDAGInfo.cpp | 52 EVT VT = MVT::i32;
67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
68 DAG.getConstant(SrcOff, MVT::i32)),
74 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
80 DAG.getConstant(DstOff, MVT::i32)),
85 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
98 VT = MVT::i16;
101 VT = MVT::i8;
106 DAG.getNode(ISD::ADD, dl, MVT::i32, Src
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 36 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
37 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
49 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
50 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
135 SDValue RetAddrOffsetNode = DAG.getConstant(RetAddrOffset, MVT::i32);
138 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain,
140 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain,
174 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
175 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
184 assert(VA.getLocVT() == MVT::f64)
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 34 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
36 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
37 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
40 std::string llvm::getName(MVT::SimpleValueType T) {
42 case MVT::Other: return "UNKNOWN";
43 case MVT::iPTR: return "TLI.getPointerTy()";
44 case MVT::iPTRAny: return "TLI.getPointerTy()";
49 std::string llvm::getEnumName(MVT::SimpleValueType T) {
51 case MVT::Other: return "MVT::Other"
[all...] |
| CodeGenTarget.h | 50 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
52 MVT::SimpleValueType getValueType(Record *Rec);
54 std::string getName(MVT::SimpleValueType T);
55 std::string getEnumName(MVT::SimpleValueType T);
70 mutable std::vector<MVT::SimpleValueType> LegalValueTypes;
126 std::vector<MVT::SimpleValueType> getRegisterVTs(Record *R) const;
128 const std::vector<MVT::SimpleValueType> &getLegalValueTypes() const {
135 bool isLegalValueType(MVT::SimpleValueType VT) const {
136 const std::vector<MVT::SimpleValueType> &LegalVTs = getLegalValueTypes();
181 MVT::SimpleValueType Ty
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 55 return CurDAG->getTargetConstant(Imm, MVT::i32);
95 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
96 Offset = CurDAG->getTargetConstant(0, MVT::i32);
105 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
106 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
117 Offset = CurDAG->getTargetConstant(0, MVT::i32);
127 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
138 Offset = CurDAG->getTargetConstant(0, MVT::i32);
148 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
166 MVT::i32, MskSize)
[all...] |
| XCoreISelLowering.cpp | 69 addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass);
86 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
87 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
88 setOperationAction(ISD::ADDC, MVT::i32, Expand);
89 setOperationAction(ISD::ADDE, MVT::i32, Expand);
90 setOperationAction(ISD::SUBC, MVT::i32, Expand);
91 setOperationAction(ISD::SUBE, MVT::i32, Expand);
94 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
97 setOperationAction(ISD::ADD, MVT::i64, Custom);
98 setOperationAction(ISD::SUB, MVT::i64, Custom)
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXISelLowering.cpp | 39 addRegisterClass(MVT::i1, PTX::RegPredRegisterClass);
40 addRegisterClass(MVT::i16, PTX::RegI16RegisterClass);
41 addRegisterClass(MVT::i32, PTX::RegI32RegisterClass);
42 addRegisterClass(MVT::i64, PTX::RegI64RegisterClass);
43 addRegisterClass(MVT::f32, PTX::RegF32RegisterClass);
44 addRegisterClass(MVT::f64, PTX::RegF64RegisterClass);
61 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Expand);
62 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
63 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
67 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand)
[all...] |
| PTXISelDAGToDAG.cpp | 95 SDValue PredOp = CurDAG->getTargetConstant(PTXPredicate::Normal, MVT::i32);
99 assert(Pred.getValueType() == MVT::i1);
103 return CurDAG->getMachineNode(PTX::BRAdp, dl, MVT::Other, Ops, 4);
114 assert(VT.isSimple() && "READ_PARAM only implemented for MVT types");
116 MVT Type = VT.getSimpleVT();
118 if (Type == MVT::i1)
120 else if (Type == MVT::i16)
122 else if (Type == MVT::i32)
124 else if (Type == MVT::i64)
126 else if (Type == MVT::f32
[all...] |
| PTXSelectionDAGInfo.cpp | 54 EVT VT = MVT::i32;
61 EVT PointerType = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
77 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
88 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
101 VT = MVT::i16;
104 VT = MVT::i8;
118 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
124 VT = MVT::i16;
127 VT = MVT::i8
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 63 return CurDAG->getTargetConstant(Imm, MVT::i32);
69 return CurDAG->getTargetConstant(Imm, MVT::i64);
240 if (PPCLowering.getPointerTy() == MVT::i32) {
263 if (N->getValueType(0) == MVT::i32)
277 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
287 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
335 if (N->getValueType(0) != MVT::i32)
437 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
450 if (LHS.getValueType() == MVT::i32) {
456 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS
[all...] |
| PPCISelLowering.cpp | 39 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
43 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
44 MVT &LocVT,
48 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
49 MVT &LocVT,
79 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
80 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
81 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote)
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 38 static bool CC_MBlaze_AssignReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
65 addRegisterClass(MVT::i32, MBlaze::GPRRegisterClass);
67 addRegisterClass(MVT::f32, MBlaze::GPRRegisterClass);
68 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
72 setOperationAction(ISD::FREM, MVT::f32, Expand);
73 setOperationAction(ISD::FMA, MVT::f32, Expand);
74 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Expand);
75 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Expand);
76 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 93 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
129 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
166 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
219 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
220 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
221 addRegisterClass(MVT::i32, X86::GR32RegisterClass)
[all...] |
| X86SelectionDAGInfo.cpp | 93 AVT = MVT::i16;
98 AVT = MVT::i32;
103 AVT = MVT::i64;
109 AVT = MVT::i8;
115 if (AVT.bitsGT(MVT::i8)) {
125 AVT = MVT::i8;
140 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
149 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
150 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 99 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
102 addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass);
105 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
110 addRegisterClass(MVT::f64, Mips::FGR64RegisterClass);
112 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
117 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
118 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
119 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
122 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
123 setTruncStoreAction(MVT::f64, MVT::f32, Expand)
[all...] |
