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    Searched refs:PassConfig (Results 1 - 8 of 8) sorted by null

  /external/llvm/include/llvm/CodeGen/
MachineScheduler.h 21 // Inside <Target>PassConfig:
46 const TargetPassConfig *PassConfig;
50 MachineSchedContext(): MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {}
  /external/llvm/lib/CodeGen/
LLVMTargetMachine.cpp 114 TargetPassConfig *PassConfig = TM->createPassConfig(PM);
116 // Set PassConfig options provided by TargetMachine.
117 PassConfig->setDisableVerify(DisableVerify);
119 PM.add(PassConfig);
121 PassConfig->addIRPasses();
125 PassConfig->addISelPrepare();
145 if (PassConfig->addInstSelector())
148 PassConfig->addMachinePasses();
150 PassConfig->setInitialized();
PostRASchedulerList.cpp 255 TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
270 if (!ST.enablePostRAScheduler(PassConfig->getOptLevel(), AntiDepMode,
MachineScheduler.cpp 146 PassConfig = &getAnalysis<TargetPassConfig>();
BranchFolding.cpp 86 TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
87 BranchFolder Folder(PassConfig->getEnableTailMerge(), /*CommonHoist=*/true);
    [all...]
  /external/llvm/lib/Target/PTX/
PTXTargetMachine.cpp 127 PTXPassConfig *PassConfig = new PTXPassConfig(this, PM);
128 PassConfig->disablePass(PrologEpilogCodeInserterID);
129 return PassConfig;
  /external/llvm/lib/Target/PowerPC/
PPCTargetMachine.cpp 90 TargetPassConfig *PassConfig = new PPCPassConfig(this, PM);
94 PassConfig->setEnableTailMerge(false);
96 return PassConfig;
  /frameworks/compile/mclinker/lib/CodeGen/
LLVMTargetMachine.cpp 143 TargetPassConfig *PassConfig = TM->createPassConfig(PM);
145 // Set PassConfig options provided by TargetMachine.
146 PassConfig->setDisableVerify(DisableVerify);
148 PM.add(PassConfig);
150 PassConfig->addIRPasses();
154 PassConfig->addISelPrepare();
174 if (PassConfig->addInstSelector())
177 PassConfig->addMachinePasses();
179 PassConfig->setInitialized();

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