| /external/llvm/lib/Target/PTX/ |
| PTXISelLowering.cpp | 253 EVT RegVT = Ins[i].VT;
254 const TargetRegisterClass* TRC = getRegClassFor(RegVT);
258 if (RegVT == MVT::i1)
260 else if (RegVT == MVT::i16)
262 else if (RegVT == MVT::i32)
264 else if (RegVT == MVT::i64)
266 else if (RegVT == MVT::f32)
268 else if (RegVT == MVT::f64)
277 SDValue ArgValue = DAG.getNode(PTXISD::READ_PARAM, dl, RegVT, Chain,
331 EVT RegVT = Outs[i].VT
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 722 MVT RegVT = VA.getLocVT();
730 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
733 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
736 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 839 EVT RegVT = VA.getLocVT();
840 if (RegVT == MVT::i8 || RegVT == MVT::i16 || RegVT == MVT::i32) {
844 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
845 } else if (RegVT == MVT::i64) {
849 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 322 EVT RegVT = VA.getLocVT();
323 switch (RegVT.getSimpleVT().SimpleTy) {
328 << RegVT.getSimpleVT().SimpleTy << "\n";
336 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
342 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
345 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 350 EVT RegVT = Value.getValueType();
351 EVT RegSclVT = RegVT.getScalarType();
|
| SelectionDAGBuilder.h | 275 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
281 EVT RegVT;
|
| SelectionDAGBuilder.cpp | 582 EVT regvt, EVT valuevt)
583 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
[all...] |
| LegalizeDAG.cpp | 320 EVT RegVT =
325 unsigned RegBytes = RegVT.getSizeInBits() / 8;
329 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
342 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
364 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
445 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
447 unsigned RegBytes = RegVT.getSizeInBits() / 8;
451 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
461 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
479 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr
[all...] |
| LegalizeIntegerTypes.cpp | 702 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
704 // The argument is passed as NumRegs registers of type RegVT.
708 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
724 DAG.getConstant(i * RegVT.getSizeInBits(),
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
