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Searched
refs:ResultReg
(Results
1 - 3
of
3
) sorted by null
/external/llvm/lib/CodeGen/SelectionDAG/
FastISel.cpp
369
unsigned
ResultReg
= FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
372
if (
ResultReg
== 0) return false;
375
UpdateValueMap(I,
ResultReg
);
405
unsigned
ResultReg
= FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
407
if (
ResultReg
== 0) return false;
410
UpdateValueMap(I,
ResultReg
);
416
unsigned
ResultReg
= FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
418
if (
ResultReg
!= 0) {
420
UpdateValueMap(I,
ResultReg
);
433
unsigned
ResultReg
= FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT()
[
all
...]
/external/llvm/lib/Target/X86/
X86FastISel.cpp
87
unsigned &
ResultReg
);
177
unsigned &
ResultReg
) {
224
ResultReg
= createResultReg(RC);
226
DL, TII.get(Opc),
ResultReg
), AM);
324
unsigned &
ResultReg
) {
329
ResultReg
= RR;
830
unsigned
ResultReg
= 0;
831
if (X86FastEmitLoad(VT, AM,
ResultReg
)) {
832
UpdateValueMap(I,
ResultReg
);
915
unsigned
ResultReg
= createResultReg(&X86::GR8RegClass)
[
all
...]
/external/llvm/lib/Target/ARM/
ARMFastISel.cpp
182
bool ARMEmitLoad(EVT VT, unsigned &
ResultReg
, Address &Addr,
290
unsigned
ResultReg
= createResultReg(RC);
293
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II,
ResultReg
));
294
return
ResultReg
;
300
unsigned
ResultReg
= createResultReg(RC);
304
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II,
ResultReg
)
310
TII.get(TargetOpcode::COPY),
ResultReg
)
313
return
ResultReg
;
320
unsigned
ResultReg
= createResultReg(RC);
324
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II,
ResultReg
)
[
all
...]
Completed in 735 milliseconds