| /external/libvpx/build/make/ |
| ads2gas.pl | 41 # Convert :SHL: to <<
42 s/:SHL:/ << /g;
|
| ads2gas_apple.pl | 59 # Convert :SHL: to <<
60 s/:SHL:/ << /g;
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 26 case ISD::SHL: return ARM_AM::lsl;
|
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| RegOps.java | 115 public static final int SHL = 23;
336 case SHL: return "shl";
|
| DexTranslationAdvice.java | 81 case RegOps.SHL:
|
| Rops.java | 339 new Rop(RegOps.SHL, Type.INT, StdTypeList.INT_INT, "shl-int");
343 new Rop(RegOps.SHL, Type.LONG, StdTypeList.LONG_INT, "shl-long");
484 new Rop(RegOps.SHL, Type.INT, StdTypeList.INT, "shl-const-int");
488 new Rop(RegOps.SHL, Type.LONG, StdTypeList.INT, "shl-const-long");
[all...] |
| /dalvik/dx/src/com/android/dx/rop/code/ |
| RegOps.java | 115 public static final int SHL = 23;
336 case SHL: return "shl";
|
| DexTranslationAdvice.java | 88 case RegOps.SHL:
|
| Rops.java | 339 new Rop(RegOps.SHL, Type.INT, StdTypeList.INT_INT, "shl-int");
343 new Rop(RegOps.SHL, Type.LONG, StdTypeList.LONG_INT, "shl-long");
484 new Rop(RegOps.SHL, Type.INT, StdTypeList.INT, "shl-const-int");
488 new Rop(RegOps.SHL, Type.LONG, StdTypeList.INT, "shl-const-long");
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| RegOps.java | 115 public static final int SHL = 23;
336 case SHL: return "shl";
|
| DexTranslationAdvice.java | 88 case RegOps.SHL:
|
| Rops.java | 339 new Rop(RegOps.SHL, Type.INT, StdTypeList.INT_INT, "shl-int");
343 new Rop(RegOps.SHL, Type.LONG, StdTypeList.LONG_INT, "shl-long");
484 new Rop(RegOps.SHL, Type.INT, StdTypeList.INT, "shl-const-int");
488 new Rop(RegOps.SHL, Type.LONG, StdTypeList.INT, "shl-const-long");
[all...] |
| /external/v8/src/ |
| token.h | 99 T(SHL, "<<", 11) \
269 return (SHL <= op) && (op <= SHR);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 345 if (Opcode == ISD::SHL) {
396 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
398 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
405 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
406 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
418 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
421 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
425 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
428 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 310 SHL, SRA, SRL, ROTL, ROTR,
374 // SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| MSP430ISelLowering.cpp | 96 setOperationAction(ISD::SHL, MVT::i8, Custom);
99 setOperationAction(ISD::SHL, MVT::i16, Custom);
183 case ISD::SHL: // FALLTHROUGH
597 case ISD::SHL:
598 return DAG.getNode(MSP430ISD::SHL, dl,
623 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 71 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
534 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
723 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
[all...] |
| DAGCombiner.cpp | [all...] |
| LegalizeDAG.cpp | 549 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
[all...] |
| /external/speex/libspeex/ |
| arch.h | 178 #define SHL(a,shift) (a)
|
| fixed_generic.h | 60 #define SHL(a,shift) ((spx_word32_t)(a) << (shift))
|
| /dalvik/dx/src/com/android/dx/ssa/ |
| SCCP.java | 437 case RegOps.SHL:
516 case RegOps.SHL:
|
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| SCCP.java | 437 case RegOps.SHL:
516 case RegOps.SHL:
|
| /external/openssl/crypto/sha/asm/ |
| sha512-ppc.pl | 46 $SHL="sldi";
54 $SHL="slwi";
187 $SHL $num,$num,`log(16*$SZ)/log(2)`
|
