| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 371 SINT_TO_FP,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 226 case ISD::SINT_TO_FP:
428 // Make sure that the SINT_TO_FP and SRL instructions are available.
429 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
455 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
457 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
|
| LegalizeDAG.cpp | 730 case ISD::SINT_TO_FP:
[all...] |
| LegalizeFloatTypes.cpp | 96 case ISD::SINT_TO_FP:
540 bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
[all...] |
| SelectionDAGDumper.cpp | 223 case ISD::SINT_TO_FP: return "sint_to_fp";
|
| LegalizeVectorTypes.cpp | 90 case ISD::SINT_TO_FP:
504 case ISD::SINT_TO_FP:
[all...] |
| FastISel.cpp | 202 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
[all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 348 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
349 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
350 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
354 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
390 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 721 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 110 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Custom);
115 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
535 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
539 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 243 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
261 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
263 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
264 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
271 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
274 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 189 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
278 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
287 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
412 setTargetDAGCombine(ISD::SINT_TO_FP);
[all...] |
