| /external/llvm/lib/Target/Hexagon/ |
| HexagonVarargsCallingConvention.h | 57 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
58 LocVT.getSimpleVT(), LocInfo));
69 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
70 LocVT.getSimpleVT(), LocInfo));
92 State.addLoc(CCValAssign::getMem(ValNo, ValVT.getSimpleVT(), Offset3,
93 LocVT.getSimpleVT(), LocInfo));
113 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
114 LocVT.getSimpleVT(), LocInfo));
125 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
126 LocVT.getSimpleVT(), LocInfo))
[all...] |
| HexagonCallingConvLower.cpp | 53 addLoc(CCValAssign::getMem(ValNo, ValVT.getSimpleVT(), Offset,
54 LocVT.getSimpleVT(), LocInfo));
|
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 195 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
207 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy];
215 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy];
223 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
224 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
242 unsigned I = VT.getSimpleVT().SimpleTy;
362 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
388 VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
390 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType];
404 assert(ValVT.getSimpleVT() < MVT::LAST_VALUETYPE &
[all...] |
| TargetCallingConv.h | 119 VT = vt.getSimpleVT();
137 VT = vt.getSimpleVT();
|
| /external/llvm/lib/Target/PTX/ |
| PTXISelDAGToDAG.cpp | 116 MVT Type = VT.getSimpleVT();
154 MVT Type = VT.getSimpleVT();
206 R2 = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
236 Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
250 Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
263 Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
299 Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
314 Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
|
| PTXISelLowering.cpp | 196 PtrVT.getSimpleVT(),
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 130 MVT VT = RealVT.getSimpleVT();
134 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
202 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
280 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND,
285 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE,
369 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
371 VT.getSimpleVT());
405 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
406 Op0IsKill, Imm, VT.getSimpleVT());
416 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT()
[all...] |
| SelectionDAG.cpp | 63 switch (VT.getSimpleVT().SimpleTy) {
655 Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != 0;
656 ValueTypeNodes[VT.getSimpleVT().SimpleTy] = 0;
[all...] |
| LegalizeDAG.cpp | 262 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 309 switch (VT.getSimpleVT().SimpleTy) {
334 MVT VT = LD->getMemoryVT().getSimpleVT();
363 MVT VT = LD->getMemoryVT().getSimpleVT();
|
| MSP430ISelLowering.cpp | 323 switch (RegVT.getSimpleVT().SimpleTy) {
328 << RegVT.getSimpleVT().SimpleTy << "\n";
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 154 VT = evt.getSimpleVT();
181 switch (VT.getSimpleVT().SimpleTy) {
238 switch (VT.getSimpleVT().SimpleTy) {
290 switch (VT.getSimpleVT().SimpleTy) {
325 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
793 SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op,
843 switch (VT.getSimpleVT().SimpleTy) {
860 switch (VT.getSimpleVT().SimpleTy)
[all...] |
| X86ISelDAGToDAG.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| X86RegisterInfo.cpp | 537 switch (VT.getSimpleVT().SimpleTy) {
|
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 452 MVT EltTy = getSimpleVT().getVectorElementType();
565 /// getSimpleVT - Return the SimpleValueType held in the specified
567 MVT getSimpleVT() const {
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 95 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
96 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
97 PromotedLdStVT.getSimpleVT());
99 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
100 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
101 PromotedLdStVT.getSimpleVT());
106 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
107 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
108 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
110 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Custom)
[all...] |
| ARMFastISel.cpp | 748 VT = evt.getSimpleVT();
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 518 switch(VT.getSimpleVT().SimpleTy){
[all...] |
| SPUISelDAGToDAG.cpp | 82 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
650 switch (Op0VT.getSimpleVT().SimpleTy) {
842 getRC( VT.getSimpleVT()), Chain);
[all...] |
| /external/llvm/utils/TableGen/ |
| IntrinsicEmitter.cpp | 255 EmitTypeForValueType(OS, VVT.getVectorElementType().getSimpleVT().SimpleTy);
|
| CodeGenDAGPatterns.cpp | 517 VTOperand.MergeInTypeInfo(IVT.getSimpleVT().SimpleTy, TP);
532 if (EVT(TypeVec[i]).getVectorElementType().getSimpleVT().SimpleTy != VT) {
561 EEVT::TypeSet EltTypeSet(IVT.getSimpleVT().SimpleTy, TP);
567 EEVT::TypeSet EltTypeSet(IVT.getSimpleVT().SimpleTy, TP);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
