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  /external/llvm/include/llvm/CodeGen/
CalcSpillWeights.h 44 LiveIntervals &LIS;
48 VirtRegAuxInfo(MachineFunction &mf, LiveIntervals &lis,
50 MF(mf), LIS(lis), Loops(loops) {}
LiveRangeEdit.h 61 LiveIntervals &LIS;
98 /// @param lis The collection of all live intervals in this function.
105 LiveIntervals &lis,
109 MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),
186 /// to erase it from LIS.
RegAllocPBQP.h 128 const LiveIntervals *lis,
149 const LiveIntervals *lis,
LiveInterval.h 289 void RenumberValues(LiveIntervals &lis);
540 /// // allocate numComps-1 new LiveIntervals into LIS[1..]
541 /// ConEQ.Distribute(LIS);
545 LiveIntervals &LIS;
554 explicit ConnectedVNInfoEqClasses(LiveIntervals &lis) : LIS(lis) {}
  /external/valgrind/main/coregrind/m_dispatch/
dispatch-ppc32-linux.S 77 lis 5,VG_(machine_ppc32_has_FP)@ha
130 lis 5,VG_(machine_ppc32_has_VMX)@ha
197 lis 5,VG_(dispatch_ctr)@ha
203 lis 5,VG_(machine_ppc32_has_FP)@ha
220 lis 5,VG_(machine_ppc32_has_VMX)@ha
261 lis 5,VG_(tt_fast)@ha
312 lis 5,VG_(tt_fast)@ha
398 lis 10,VG_(machine_ppc32_has_FP)@ha
414 lis 11,VG_(machine_ppc32_has_VMX)@ha
449 lis 5,VG_(dispatch_ctr)@h
    [all...]
  /external/llvm/lib/CodeGen/
Spiller.cpp 55 LiveIntervals *lis; member in class:__anon8981::SpillerBase
65 lis = &pass.getAnalysis<LiveIntervals>();
140 lis->InsertMachineInstrInMaps(loadInstr).getRegSlot();
143 newLI->getNextValue(loadIndex, lis->getVNInfoAllocator());
153 lis->InsertMachineInstrInMaps(storeInstr).getRegSlot();
156 newLI->getNextValue(beginIndex, lis->getVNInfoAllocator());
CalcSpillWeights.cpp 48 LiveIntervals &lis = getAnalysis<LiveIntervals>(); local
49 VirtRegAuxInfo vrai(fn, lis, getAnalysis<MachineLoopInfo>());
50 for (LiveIntervals::iterator I = lis.begin(), E = lis.end(); I != E; ++I) {
132 if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb))
146 if (hweight > bestPhys && LIS.isAllocatable(hint))
168 if (li.isZeroLength(LIS.getSlotIndexes())) {
179 if (LIS.isReMaterializable(li, 0, isLoad)) {
RegAllocPBQP.cpp 140 LiveIntervals *lis; member in class:__anon8952::RegAllocPBQP
194 const LiveIntervals *lis,
199 ArrayRef<SlotIndex> regMaskSlots = lis->getRegMaskSlots();
208 for (LiveIntervals::const_iterator itr = lis->begin(), end = lis->end();
223 const LiveInterval *vregLI = &lis->getInterval(vreg);
243 const LiveInterval *pregLI = &lis->getInterval(preg);
260 MachineInstr *rmMI = lis->getInstructionFromIndex(rmIdx);
323 const LiveInterval &l1 = lis->getInterval(vr1);
329 const LiveInterval &l2 = lis->getInterval(vr2)
    [all...]
RenderMachineFunction.h 63 LiveIntervals *lis, const RenderMachineFunction *rmf);
119 LiveIntervals *lis; member in class:llvm::MFRenderingOptions
142 const TargetRegisterInfo *tri, LiveIntervals *lis);
171 LiveIntervals *lis; member in class:llvm::TargetRegisterExtraInfo
248 LiveIntervals *lis; member in class:llvm::RenderMachineFunction
InterferenceCache.h 56 /// LIS - Used for accessing register mask interference maps.
57 LiveIntervals *LIS;
78 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {}
80 void clear(MachineFunction *mf, SlotIndexes *indexes, LiveIntervals *lis) {
85 LIS = lis;
RenderMachineFunction.cpp 196 LiveIntervals *lis,
200 this->lis = lis;
269 for (LiveIntervals::iterator liItr = lis->begin(), liEnd = lis->end();
296 if (lis->hasInterval(reg)) {
297 intervalSet.insert(&lis->getInterval(reg));
316 LiveIntervals *lis) {
320 this->lis = lis;
    [all...]
RegAllocBase.h 95 LiveIntervals *LIS;
98 RegAllocBase(): UserTag(0), TRI(0), MRI(0), VRM(0), LIS(0) {}
103 void init(VirtRegMap &vrm, LiveIntervals &lis);
InterferenceCache.cpp 28 LiveIntervals *lis,
35 Entries[i].clear(mf, indexes, lis);
145 RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum);
146 RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum);
SplitKit.h 45 const LiveIntervals &LIS;
119 SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
212 LiveIntervals &LIS;
RegAllocBase.cpp 69 for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
99 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
104 LIS = &lis;
136 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
177 LIS->removeInterval(VirtReg->reg);
222 LIS->removeInterval(SplitVirtReg->reg);
248 SlotIndexes *Indexes = LIS->getSlotIndexes()
    [all...]
SplitKit.cpp 43 const LiveIntervals &lis,
47 LIS(lis),
65 SlotIndex MBBEnd = LIS.getMBBEndIdx(MBB);
74 LSP.first = LIS.getInstructionIndex(FirstTerm);
85 LSP.second = LIS.getInstructionIndex(I);
93 if (!LPad || !LSP.second || !LIS.isLiveInToMBB(*CurLI, LPad))
116 if (LSP == LIS.getMBBEndIdx(MBB))
118 return LIS.getInstructionFromIndex(LSP);
138 UseSlots.push_back(LIS.getInstructionIndex(&*I).getRegSlot())
    [all...]
  /external/valgrind/main/exp-bbv/tests/ppc32-linux/
million.S 8 lis 15,499997@ha # load high 16-bits of counter
ll.S 53 # as we can just do an addi rather than an lis;addi
55 lis 25,bss_begin@ha
58 lis 26,data_begin@ha
230 lis 20,('l'<<8)+'o' # find 'lock ' and grab up to M
244 lis 20,('c'<<8)+'p' # find 'cpu\t: ' and grab up to \n
280 lis 20,('m'<<8)+'i' # find 'mips' and grab up to \n
402 lis 4,escape@ha
410 lis 4,c@ha
420 lis 4,linefeed@ha
  /frameworks/base/core/java/android/view/
OrientationEventListener.java 78 void registerListener(OrientationListener lis) {
79 mOldListener = lis;
  /external/libffi/src/powerpc/
asm.h 68 lis %r11,0b@ha; \
  /external/openssl/crypto/sha/asm/
sha1-ppc.pl 279 lis $K,0x5a82
284 lis $K,0x6ed9
289 lis $K,0x8f1b
294 lis $K,0xca62
  /external/flac/libFLAC/ppc/gas/
lpc_asm.s 148 lis r31,L1305@ha
162 lis r31,L1304@ha
176 lis r31,L1303@ha
190 lis r31,L1302@ha
204 lis r31,L1301@ha
216 lis r31,L1300@ha
369 lis r31,L2301@ha
381 lis r31,L2300@ha
  /external/libvpx/vp8/common/ppc/
idctllm_altivec.asm 15 lis \R0, \LABEL@ha
  /system/extras/librank/
librank.c 181 struct library_info *li, **lis; local
  /external/libvpx/vp8/encoder/ppc/
fdct_altivec.asm 16 lis \R0, \LABEL@ha

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