| /external/llvm/test/CodeGen/X86/ |
| widen_conv-4.ll | 6 define void @convert(<7 x float>* %dst.addr, <7 x i16> %src) nounwind {
8 %val = sitofp <7 x i16> %src to <7 x float>
|
| x86-64-arg.ll | 10 define i32 @test(i16 signext %X) {
12 %tmp12 = sext i16 %X to i32 ; <i32> [#uses=1]
|
| 2009-04-13-2AddrAssert.ll | 5 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
11 %conv = trunc i32 %call to i16 ; <i16> [#uses=1]
12 %0 = tail call i16 asm "xchgb ${0:h}, ${0:b}","=Q,0,~{dirflag},~{fpsr},~{flags}"(i16 %conv) nounwind ; <i16> [#uses=0]
|
| dagcombine-buildvector.ll | 18 define void @test2(<4 x i16>* %src, <4 x i32>* %dest) nounwind {
20 %tmp1 = load <4 x i16>* %src
21 %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
22 %0 = tail call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3)
27 declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone
|
| fast-isel-ret-ext.ll | 18 define zeroext i16 @test3(i32 %y) nounwind {
19 %conv = trunc i32 %y to i16
20 ret i16 %conv
25 define signext i16 @test4(i32 %y) nounwind {
26 %conv = trunc i32 %y to i16
27 ret i16 %conv
|
| lsr-sort.ll | 5 @X = common global i16 0 ; <i16*> [#uses=1]
14 %1 = trunc i32 %i.03 to i16 ; <i16> [#uses=1]
15 store volatile i16 %1, i16* @X, align 2
|
| narrow_op-1.ll | 6 %struct.bf = type { i64, i16, i16, i32 }
11 %0 = load i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
13 store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
19 %0 = load i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
21 store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
|
| vec_insert-2.ll | 35 define <8 x i16> @t4(i16 %s, <8 x i16> %tmp) nounwind {
40 %tmp1 = insertelement <8 x i16> %tmp, i16 %s, i32 5
41 ret <8 x i16> %tmp1
|
| avx2-arith.ll | 16 define <16 x i16> @vpaddw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
17 %x = add <16 x i16> %i, %j
18 ret <16 x i16> %x
40 define <16 x i16> @vpsubw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
41 %x = sub <16 x i16> %i, %j
42 ret <16 x i16> %
[all...] |
| /external/llvm/test/DebugInfo/X86/ |
| subreg.ll | 9 define i16 @f(i16 signext %zzz) nounwind {
11 call void @llvm.dbg.value(metadata !{i16 %zzz}, i64 0, metadata !0)
12 %conv = sext i16 %zzz to i32, !dbg !7
13 %conv1 = trunc i32 %conv to i16
14 ret i16 %conv1
20 !1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"f", metadata !"f", metadata !"", metadata !2, i32 3, metadata !4, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i16 (i16)* @f, null, null} ; [ DW_TAG_subprogram ]
|
| /external/llvm/test/ExecutionEngine/ |
| test-loadstore.ll | 4 define void @test(i8* %P, i16* %P.upgrd.1, i32* %P.upgrd.2, i64* %P.upgrd.3) {
7 %V.upgrd.4 = load i16* %P.upgrd.1 ; <i16> [#uses=1]
8 store i16 %V.upgrd.4, i16* %P.upgrd.1
26 %B = alloca i16 ; <i16*> [#uses=1]
29 call void @test( i8* %A, i16* %B, i32* %C, i64* %D )
|
| test-logical.ll | 7 %A.upgrd.1 = and i16 4, 8 ; <i16> [#uses=2]
8 %B.upgrd.2 = or i16 %A.upgrd.1, 7 ; <i16> [#uses=1]
9 %C.upgrd.3 = xor i16 %B.upgrd.2, %A.upgrd.1 ; <i16> [#uses=0]
|
| /external/llvm/test/Transforms/InstCombine/ |
| pr2996.ll | 4 define void @func_53(i16 signext %p_56) nounwind {
6 %0 = icmp sgt i16 %p_56, -1 ; <i1> [#uses=1]
|
| /external/llvm/test/CodeGen/ARM/ |
| vminmax.ll | 12 define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
15 %tmp1 = load <4 x i16>* %A
16 %tmp2 = load <4 x i16>* %B
17 %tmp3 = call <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
18 ret <4 x i16> %tmp3
39 define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind
[all...] |
| vst3.ll | 13 define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind {
16 %tmp0 = bitcast i16* %A to i8*
17 %tmp1 = load <4 x i16>* %B
18 call void @llvm.arm.neon.vst3.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
75 define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind {
79 %tmp0 = bitcast i16* %A to i8
[all...] |
| 2009-07-22-ScavengerAssert.ll | 3 %struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* }
5 %struct.cli_ac_patt = type { i16*, i16*, i16, i16, i8, i32, i32, i8*, i8*, i32, i16, i16, i16, i16, %struct.cli_ac_alt**, i8, i16, %struct.cli_ac_patt*, %struct.cli_ac_patt*
[all...] |
| rev.ll | 23 %tmp1.upgrd.1 = trunc i32 %tmp1 to i16
24 %tmp3 = trunc i32 %X to i16
25 %tmp2 = and i16 %tmp1.upgrd.1, 255
26 %tmp4 = shl i16 %tmp3, 8
27 %tmp5 = or i16 %tmp2, %tmp4
28 %tmp5.upgrd.2 = sext i16 %tmp5 to i32
33 define i32 @test3(i16 zeroext %a) nounwind {
37 %0 = tail call i16 @llvm.bswap.i16(i16 %a
[all...] |
| vector-DAGCombine.ll | 65 ; operands with i16 elements.
68 %0 = sext <4 x i1> zeroinitializer to <4 x i16>
69 %1 = add <4 x i16> %0, zeroinitializer
70 %2 = shufflevector <4 x i16> %1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
71 %3 = add <8 x i16> %2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| 2006-11-29-AltivecFPSplat.ll | 5 %tmp3030030304.i = bitcast <4 x float> %tmp26355.i to <8 x i16> ; <<8 x i16>> [#uses=1]
6 %tmp30305.i = shufflevector <8 x i16> zeroinitializer, <8 x i16> %tmp3030030304.i, <8 x i32> < i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15 > ; <<8 x i16>> [#uses=1]
7 %tmp30305.i.upgrd.1 = bitcast <8 x i16> %tmp30305.i to <4 x i32> ; <<4 x i32>> [#uses=1]
|
| delete-node.ll | 7 define void @GrayATo32ARGBTabB(i8* %baseAddr, i16** %cmp, i32 %rowBytes) nounwind {
12 %0 = load i16* null, align 2 ; <i16> [#uses=1]
13 %1 = ashr i16 %0, 4 ; <i16> [#uses=1]
14 %2 = sext i16 %1 to i32 ; <i32> [#uses=1]
|
| ppcf128-3.ll | 4 define i32 @stp_sequence_set_short_data(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
6 %tmp1112 = sitofp i16 0 to ppc_fp128 ; <ppc_fp128> [#uses=1]
11 define i32 @stp_sequence_set_short_data2(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
18 define i32 @stp_sequence_set_short_data3(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
20 %tmp1112 = uitofp i16 0 to ppc_fp128 ; <ppc_fp128> [#uses=1]
25 define i32 @stp_sequence_set_short_data4(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
|
| /external/llvm/test/Transforms/GVN/ |
| crash-no-aa.ll | 3 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v1
8 define i32 @test1({i16, i32} *%P) {
9 %P2 = getelementptr {i16, i32} *%P, i32 0, i32 0
10 store i16 42, i16* %P2
12 %P3 = getelementptr {i16, i32} *%P, i32 0, i32 1
|
| /external/llvm/test/Transforms/LoopUnswitch/ |
| 2008-06-17-DomFrontier.ll | 2 @g_56 = external global i16 ; <i16*> [#uses=2]
17 store i16 0, i16* @g_56, align 2
20 %tmp46 = load i16* @g_56, align 2 ; <i16> [#uses=0]
|
| /external/llvm/test/Transforms/ScalarRepl/ |
| 2009-03-04-MemCpyAlign.ll | 3 ; RUN: opt < %s -scalarrepl -S | grep {store i16 1, .*, align 1}
5 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
7 %struct.st = type { i16 }
12 %0 = getelementptr %struct.st* %s, i32 0, i32 0 ; <i16*> [#uses=1]
13 store i16 1, i16* %0, align 4
|
| /external/llvm/test/CodeGen/Generic/ |
| 2007-05-15-InfiniteRecursion.ll | 5 %struct.AVCodecContext = type { %struct.AVClass*, i32, i32, i32, i32, i32, i8*, i32, %struct.AVRational, i32, i32, i32, i32, i32, void (%struct.AVCodecContext*, %struct.AVFrame*, i32*, i32, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, float, float, i32, i32, i32, i32, float, i32, i32, i32, %struct.AVCodec*, i8*, i32, i32, void (%struct.AVCodecContext*, i8*, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, [32 x i8], i32, i32, i32, i32, i32, i32, i32, float, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, void (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i8*, i8*, float, float, i32, %struct.RcOverride*, i32, i8*, i32, i32, i32, float, float, float, float, i32, float, float, float, float, float, i32, i32, i32, i32*, i32, i32, i32, i32, %struct.AVRational, %struct.AVFrame*, i32, i32, [4 x i64], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32*)*, i32, i32, i32, i32, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i16*, i16*, i32, i32, i32, i32, %struct.AVPaletteControl*, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32 (%struct.AVCodecContext*, i8*)*, i8**, i32*, i32)*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64 }
7 %struct.AVFrame = type { [4 x i8*], [4 x i32], [4 x i8*], i32, i32, i64, i32, i32, i32, i32, i32, i8*, i32, i8*, [2 x [2 x i16]*], i32*, i8, i8*, [4 x i64], i32, i32, i32, i32, i32, %struct.AVPanScan*, i32, i32, i16*, [2 x i8*] }
10 %struct.AVPanScan = type { i32, i32, i32, [3 x [2 x i16]] }
12 %struct.DSPContext = type { void (i16*, i8*, i32)*, void (i16*, i8*, i8*, i32)*, void (i16*, i8*, i32)*, void (i16*, i8*, i32)*, void (i16*, i8*, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, void (i8*, i8*, i32, i32, i32, i32, (…)
[all...] |
