| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 190 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
[all...] |
| X86FastISel.cpp | 86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
179 unsigned Opc = 0;
185 Opc = X86::MOV8rm;
189 Opc = X86::MOV16rm;
193 Opc = X86::MOV32rm;
198 Opc = X86::MOV64rm;
203 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
206 Opc = X86::LD_Fp32m;
212 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
215 Opc = X86::LD_Fp64m
[all...] |
| X86InstrMMX.td | 26 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
28 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
34 def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
41 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
44 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
48 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
61 multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
63 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
67 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
75 multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr
[all...] |
| X86InstrInfo.cpp | [all...] |
| X86InstrSSE.td | 142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d
[all...] |
| /external/llvm/include/llvm/ |
| Operator.h | 149 static bool isPossiblyExactOpcode(unsigned OpC) {
150 return OpC == Instruction::SDiv ||
151 OpC == Instruction::UDiv ||
152 OpC == Instruction::AShr ||
153 OpC == Instruction::LShr;
192 template<typename SuperClass, unsigned Opc>
196 static inline bool classof(const ConcreteOperator<SuperClass, Opc> *) {
200 return I->getOpcode() == Opc;
203 return CE->getOpcode() == Opc;
|
| InstrTypes.h | 177 #define HANDLE_BINARY_INST(N, OPC, CLASS) \
178 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
180 return Create(Instruction::OPC, V1, V2, Name);\
183 #define HANDLE_BINARY_INST(N, OPC, CLASS) \
184 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
186 return Create(Instruction::OPC, V1, V2, Name, BB);\
189 #define HANDLE_BINARY_INST(N, OPC, CLASS) \
190 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
192 return Create(Instruction::OPC, V1, V2, Name, I);\
196 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2
[all...] |
| Instruction.h | 292 #define HANDLE_TERM_INST(N, OPC, CLASS) OPC = N,
299 #define HANDLE_BINARY_INST(N, OPC, CLASS) OPC = N,
306 #define HANDLE_MEMORY_INST(N, OPC, CLASS) OPC = N,
313 #define HANDLE_CAST_INST(N, OPC, CLASS) OPC = N,
320 #define HANDLE_OTHER_INST(N, OPC, CLASS) OPC = N
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | 402 unsigned Opc = N.getOpcode();
405 if (Opc == ISD::FrameIndex) {
416 } else if (Opc == ISD::ADD) {
469 } else if (Opc == SPUISD::IndirectAddr) {
500 } else if (Opc == SPUISD::AFormAddr) {
504 } else if (Opc == SPUISD::LDRESULT) {
508 } else if (Opc == ISD::Register
509 ||Opc == ISD::CopyFromReg
510 ||Opc == ISD::UNDEF
511 ||Opc == ISD::Constant)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1RegisterInfo.cpp | 128 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
130 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
131 if (Opc != ARM::tADDhirr)
142 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
147 if (Opc == ARM::tADDrSPi) {
181 int Opc = 0;
189 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
202 Opc = ARM::tADDrSPi;
211 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
216 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8
[all...] |
| ARMInstrInfo.h | 33 // Return the non-pre/post incrementing version of 'Opc'. Return 0
35 unsigned getUnindexedOpcode(unsigned Opc) const;
|
| Thumb1InstrInfo.h | 32 // Return the non-pre/post incrementing version of 'Opc'. Return 0
34 unsigned getUnindexedOpcode(unsigned Opc) const;
|
| ARMFastISel.cpp | 517 unsigned Opc;
520 Opc = ARM::FCONSTD;
523 Opc = ARM::FCONSTS;
526 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
543 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
546 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
562 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
565 TII.get(Opc), ImmReg)
576 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
579 TII.get(Opc), ImmReg
[all...] |
| ARMInstrThumb2.td | 258 string opc, string asm, list<dag> pattern>
259 : T2I<oops, iops, itin, opc, asm, pattern> {
271 string opc, string asm, list<dag> pattern>
272 : T2sI<oops, iops, itin, opc, asm, pattern> {
284 string opc, string asm, list<dag> pattern>
285 : T2I<oops, iops, itin, opc, asm, pattern> {
297 string opc, string asm, list<dag> pattern>
298 : T2I<oops, iops, itin, opc, asm, pattern> {
310 string opc, string asm, list<dag> pattern>
311 : T2sI<oops, iops, itin, opc, asm, pattern>
[all...] |
| /dalvik/dexopt/ |
| OptMain.cpp | 133 const char* opc; local
136 opc = strstr(dexoptFlagStr, "v="); /* verification */
137 if (opc != NULL) {
138 switch (*(opc+2)) {
146 opc = strstr(dexoptFlagStr, "o="); /* optimization */
147 if (opc != NULL) {
148 switch (*(opc+2)) {
157 opc = strstr(dexoptFlagStr, "m=y"); /* register map */
158 if (opc != NULL) {
162 opc = strstr(dexoptFlagStr, "u="); /* uniprocessor target *
[all...] |
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| MallocOverflowSecurityChecker.cpp | 74 BinaryOperatorKind opc = binop->getOpcode(); local
76 if (mulop == NULL && opc == BO_Mul)
78 if (opc != BO_Mul && opc != BO_Add && opc != BO_Sub && opc != BO_Shl)
85 else if ((opc == BO_Add || opc == BO_Mul)
|
| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.h | 20 unsigned Opc, ImmOpnd;
21 Inst(unsigned Opc, unsigned ImmOpnd);
|
| MipsAnalyzeImmediate.cpp | 15 MipsAnalyzeImmediate::Inst::Inst(unsigned O, unsigned I) : Opc(O), ImmOpnd(I) {}
88 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) ||
89 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16))
100 Seq[0].Opc = LUi;
|
| MipsISelDAGToDAG.cpp | 89 std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
341 MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
344 SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
389 unsigned Opc = InFlag.getOpcode(); (void)Opc;
390 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
391 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
498 if (Inst->Opc == Mips::LUi64
[all...] |
| /external/qemu/tcg/arm/ |
| tcg-target.c | 298 #define TO_CPSR(opc) \
299 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
385 int cond, int opc, int rd, int rn, int rm, int shift)
387 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
411 int cond, int opc, int rd, int rn, int im)
413 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
435 int opc = ARITH_MOV; local
[all...] |
| /external/qemu/ |
| translate.make | 19 OPC_H := $(INTERMEDIATE)/opc$(OP_SUFFIX).h
|
| /external/wpa_supplicant_6/wpa_supplicant/src/hlr_auc_gw/ |
| milenage.c | 33 * @opc: OPc = 128-bit value derived from OP and K
42 static int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand,
50 tmp1[i] = _rand[i] ^ opc[i];
63 tmp3[(i + 8) % 16] = tmp2[i] ^ opc[i];
73 tmp1[i] ^= opc[i];
84 * @opc: OPc = 128-bit value derived from OP and K
94 static int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand,
102 tmp1[i] = _rand[i] ^ opc[i]
356 u8 opc[16]; member in struct:gsm_milenage_test_set
585 u8 opc[16]; member in struct:milenage_test_set
1025 u8 buf[16], buf2[16], buf3[16], buf4[16], buf5[16], opc[16]; local
[all...] |
| /external/qemu/tcg/ppc64/ |
| tcg-target.c | 275 #define OPCD(opc) ((opc)<<26)
276 #define XO19(opc) (OPCD(19)|((opc)<<1))
277 #define XO30(opc) (OPCD(30)|((opc)<<2))
278 #define XO31(opc) (OPCD(31)|((opc)<<1))
279 #define XO58(opc) (OPCD(58)|(opc))
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 422 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
426 return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
429 return DAG.getNode(Opc, dl, MVT::Other, Chain);
588 unsigned Opc = Op.getOpcode();
595 switch (Opc) {
615 if (Opc == ISD::SRL && ShiftAmount) {
623 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
[all...] |
| /external/openssl/crypto/bio/ |
| bss_log.c | 122 #define LOG_DAEMON OPC$M_NM_NTWORK
357 opcdef_p->opc$b_ms_type = OPC$_RQ_RQST;
358 memcpy(opcdef_p->opc$z_ms_target_classes, &VMS_OPC_target, 3);
359 opcdef_p->opc$l_ms_rqstid = 0;
360 memcpy(&opcdef_p->opc$l_ms_text, buf, len);
|
