| /dalvik/vm/mterp/x86/ |
| OP_MONITOR_EXIT.S | 19 SPILL(rIBASE)
|
| bindiv.S | 12 SPILL(rIBASE)
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| bindiv2addr.S | 8 SPILL(rIBASE)
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| bindivLit8.S | 9 SPILL(rIBASE)
|
| entry.S | 34 * for 9 spill slots, 4 local slots, 5 arg slots to bring
39 /* Spill callee save regs */
|
| OP_CONST_CLASS.S | 29 SPILL(rIBASE)
|
| OP_CONST_STRING.S | 28 SPILL(rIBASE)
|
| OP_CONST_STRING_JUMBO.S | 28 SPILL(rIBASE)
|
| OP_DIV_LONG.S | 6 SPILL(rIBASE) # save rIBASE/%edx
|
| OP_DIV_LONG_2ADDR.S | 7 SPILL(rIBASE) # save rIBASE/%edx
|
| OP_SGET.S | 36 SPILL(rIBASE)
|
| OP_SGET_WIDE.S | 37 SPILL(rIBASE)
|
| OP_SPUT.S | 36 SPILL(rIBASE)
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| OP_SPUT_WIDE.S | 38 SPILL(rIBASE)
|
| /external/llvm/lib/CodeGen/ |
| Spiller.cpp | 72 /// Add spill ranges for every use/def of the live interval, inserting loads
81 "Attempting to spill already spilled value.");
84 "Trying to spill a stack slot.");
86 DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n");
167 /// Spills any live range using the spill-everywhere method with no attempt at
176 void spill(LiveRangeEdit &LRE) { function in class:__anon8982::TrivialSpiller
|
| RegAllocBasic.cpp | 58 /// algorithm. It prioritizes live virtual registers by spill weight and spills
189 // Spill the extracted interval.
191 spiller().spill(LRE);
198 // Spill or split all live virtual registers currently unified under PhysReg
218 // Spill each interfering vreg allocated to PhysReg or an alias.
242 // Populate a list of physical register spill candidates.
269 // must have less spill weight.
274 // Try to spill another interfering reg with less spill weight.
281 "Interference after spill.")
[all...] |
| StackSlotColoring.cpp | 55 // SSIntervals - Spill slot intervals.
58 // SSRefs - Keep a list of frame index references for each spill slot.
67 // AllColors - If index is set, it's a spill slot, i.e. color.
68 // FIXME: This assumes PEI locate spill slot with smaller indices
135 /// ScanForSpillSlotRefs - Scan all the machine instructions for spill slot
136 /// references and update spill slot weights.
166 /// InitializeSlots - Process all spill stack slot liveintervals and add them
176 // Gather all spill slots into a list.
177 DEBUG(dbgs() << "Spill slot intervals:\n");
232 assert(NextColor != -1 && "No more spill slots?")
[all...] |
| CalcSpillWeights.cpp | 29 "Calculate spill weights", false, false)
33 "Calculate spill weights", false, false)
44 DEBUG(dbgs() << "********** Compute Spill Weights **********\n"
106 // Don't recompute spill weight for an unspillable register.
159 // Weakly boost the spill weight of hinted registers.
|
| /external/valgrind/main/VEX/priv/ |
| host_generic_reg_alloc2.c | 51 providing we can arrange for the dst to have the same spill slot.
66 /* The "home" spill slot, if needed. Never changes. */
103 spill. */
106 rreg has the same value as the spill slot for the associated
108 spill store or reload for this rreg. */
164 sequence. Point is to select a virtual register to spill, by
170 caller to arbitrarily restrict the set of spill candidates to be
174 spill, or -1 if none was found. */
207 /* Check that this vreg has been assigned a sane spill offset. */
326 /* Return one, or, if we're unlucky, two insn(s) to spill/restore
[all...] |
| /external/llvm/test/CodeGen/Thumb2/ |
| aligned-spill.ll | 7 ; This function is forced to spill a double.
8 ; Verify that the spill slot is properly aligned.
33 ; Since the spill slot is only 8 bytes, technically it would be fine to only
47 ; Spill 7 d-registers.
71 ; Spill 7 d-registers, leave a hole.
|
| /external/llvm/include/llvm/CodeGen/ |
| LiveStackAnalysis.h | 60 assert(Slot >= 0 && "Spill slot indice must be >= 0");
67 assert(Slot >= 0 && "Spill slot indice must be >= 0");
78 assert(Slot >= 0 && "Spill slot indice must be >= 0");
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUFrameLowering.h | 46 //! Return a function's saved spill slots
48 For CellSPU, a function's saved spill slots is just the link register.
69 //! Minimum frame size (enough to spill LR + SP)
|
| /external/llvm/lib/Target/X86/ |
| X86CompilationCallback_Win64.asm | 24 ; WARNING: We cannot use register spill area - we're generating stubs by hands!
33 ; Save all XMM arg registers. Also allocate reg spill area.
|
| /external/llvm/test/CodeGen/ARM/ |
| 2010-05-18-LocalAllocCrash.ll | 3 ;; This test would spill %R4 before the call to zz, but it forgot to move the
4 ; 'last use' marker to the spill.
|
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 94 // Integer spill area is handled with "pop".
148 // Determine the sizes of each callee-save spill areas and record which frame
149 // belongs to which callee-save spill areas.
209 // For iOS, FP is R7, which has now been stored in spill area 1.
211 // into spill area 1, including the FP in R11. In either case, it is
226 // Determine starting offsets of spill areas.
371 // Move SP to start of FP callee save spill area.
527 // since it's available. This is handy for the emergency spill slot, in
713 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
715 /// pointer pointing to the d8 spill slot
[all...] |
