| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 99 if (Addr.getOpcode() == ISD::ADD) {
120 if (Addr.getOpcode() == ISD::ADD) {
141 if (Addr.getOpcode() == ISD::ADD) {
159 case ISD::Constant: {
214 case ISD::INTRINSIC_WO_CHAIN: {
224 case ISD::BRIND:
242 if (Chain->getOpcode() != ISD::TokenFactor)
256 return CurDAG->getNode(ISD::TokenFactor, Chain->getDebugLoc(), MVT::Other,
265 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
296 nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 403 return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
414 return getNode(ISD::CopyToReg, dl, VTs, Ops, Glue.getNode() ? 4 : 3);
422 return getNode(ISD::CopyToReg, dl, VTs, Ops, Glue.getNode() ? 4 : 3);
428 return getNode(ISD::CopyFromReg, dl, VTs, Ops, 2);
438 return getNode(ISD::CopyFromReg, dl, VTs, Ops, Glue.getNode() ? 3 : 2);
441 SDValue getCondCode(ISD::CondCode Cond);
447 SDValue Rnd, SDValue Sat, ISD::CvtCode Code);
449 /// getVectorShuffle - Return an ISD::VECTOR_SHUFFLE node. The number of
481 return getNode(ISD::CALLSEQ_START, DebugLoc(), VTs, Ops, 2);
495 return getNode(ISD::CALLSEQ_END, DebugLoc(), NodeTys, &Ops[0]
[all...] |
| ISDOpcodes.h | 19 /// ISD namespace - This namespace contains an enum which represents all of the
22 namespace ISD {
25 /// ISD::NodeType enum - This enum defines the target-independent operators
436 // 5) ISD::CvtCode indicating the type of conversion to do
698 /// ISD::CondCode enum - These are ordered carefully to make the bitfields
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | 206 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
216 ISD::CondCode CC;
480 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
481 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
482 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
484 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
485 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
486 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
487 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
488 void visitFRem(const User &I) { visitBinary(I, ISD::FREM);
[all...] |
| ResourcePriorityQueue.cpp | 88 case ISD::TokenFactor: break;
89 case ISD::CopyFromReg: NumberDeps++; break;
90 case ISD::CopyToReg: break;
91 case ISD::INLINEASM: break;
125 case ISD::TokenFactor: break;
126 case ISD::CopyFromReg: break;
127 case ISD::CopyToReg: NumberDeps++; break;
128 case ISD::INLINEASM: break;
457 case ISD::TokenFactor:
458 case ISD::CopyFromReg
[all...] |
| SelectionDAGISel.cpp | 527 if (N->getOpcode() != ISD::CopyToReg)
743 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
[all...] |
| InstrEmitter.cpp | 96 if (User->getOpcode() == ISD::CopyToReg &&
177 if (User->getOpcode() == ISD::CopyToReg &&
212 if (User->getOpcode() == ISD::CopyToReg &&
315 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
439 if (User->getOpcode() == ISD::CopyToReg &&
766 if (F->getOpcode() == ISD::CopyFromReg) {
769 } else if (F->getOpcode() == ISD::CopyToReg) {
[all...] |
| LegalizeTypes.cpp | [all...] |
| ScheduleDAGRRList.cpp | 396 if (N->getOpcode() == ISD::TokenFactor) {
422 if (N->getOpcode() == ISD::EntryToken)
443 if (N->getOpcode() == ISD::TokenFactor) {
482 if (N->getOpcode() == ISD::EntryToken)
656 case ISD::MERGE_VALUES:
657 case ISD::TokenFactor:
658 case ISD::CopyToReg:
659 case ISD::CopyFromReg:
660 case ISD::EH_LABEL:
664 case ISD::INLINEASM
[all...] |
| ScheduleDAGSDNodes.h | 67 if (Node->getOpcode() == ISD::EntryToken ||
|
| ScheduleDAGSDNodes.cpp | 114 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
357 if (NI->getOpcode() == ISD::TokenFactor)
379 if (SUNode->getOpcode() != ISD::CopyToReg)
453 if(isChain && OpN->getOpcode() == ISD::TokenFactor)
499 if (Node->getOpcode() == ISD::CopyFromReg)
558 if (N && N->getOpcode() == ISD::TokenFactor) {
600 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg &&
|
| LegalizeTypes.h | 78 return N->getOpcode() == ISD::TargetConstant;
201 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
288 void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);
362 ISD::CondCode &CCCode, DebugLoc dl);
435 ISD::CondCode &CCCode, DebugLoc dl);
491 ISD::CondCode &CCCode, DebugLoc dl);
658 LoadSDNode *LD, ISD::LoadExtType ExtType);
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 108 static ISD::NodeType getExtendForContent(BooleanContent Content) {
112 return ISD::ANY_EXTEND;
115 return ISD::ZERO_EXTEND;
118 return ISD::SIGN_EXTEND;
387 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
424 assert(IdxMode < ISD::LAST_INDEXED_MODE &&
445 assert(IdxMode < ISD::LAST_INDEXED_MODE &&
464 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
476 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
592 bool hasTargetDAGCombine(ISD::NodeType NT) const
[all...] |
| TargetCallingConv.h | 23 namespace ISD {
|
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 60 ISD::ArgFlagsTy &ArgFlags,
108 ISD::ArgFlagsTy &ArgFlags,
140 ISD::ArgFlagsTy &ArgFlags,
151 ISD::ArgFlagsTy &ArgFlags,
|
| ARMISelDAGToDAG.cpp | 292 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
352 if (Use->getOpcode() == ISD::CopyToReg)
448 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
450 if (N.getOpcode() == ISD::FrameIndex) {
460 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
470 if (N.getOpcode() == ISD::SUB)
475 if (Base.getOpcode() == ISD::FrameIndex) {
494 if (N.getOpcode() == ISD::MUL &&
518 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 302 if (N.getOpcode() != ISD::LOAD)
314 case ISD::ADD:
315 case ISD::ADDC:
316 case ISD::ADDE:
317 case ISD::AND:
318 case ISD::OR:
319 case ISD::XOR: {
348 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
367 assert(Chain.getOpcode() == ISD::TokenFactor &&
375 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc()
[all...] |
| X86ISelLowering.h | 32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
321 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
507 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
680 const SmallVectorImpl<ISD::InputArg> &Ins,
685 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
692 ISD::ArgFlagsTy Flags) const;
704 const SmallVectorImpl<ISD::OutputArg> &Outs,
706 const SmallVectorImpl<ISD::InputArg> &Ins,
751 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
[all...] |
| X86SelectionDAGInfo.cpp | 148 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
164 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
248 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
250 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
258 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
| X86FastISel.cpp | 86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
321 /// ISD::SIGN_EXTEND).
322 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
739 SmallVector<ISD::OutputArg, 4> Outs;
791 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
792 ISD::SIGN_EXTEND;
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonVarargsCallingConvention.h | 22 ISD::ArgFlagsTy ArgFlags,
31 ISD::ArgFlagsTy ArgFlags,
100 ISD::ArgFlagsTy ArgFlags,
|
| /external/llvm/lib/Target/PTX/ |
| PTXISelDAGToDAG.cpp | 76 case ISD::BRCOND:
82 case ISD::FrameIndex:
98 assert(Target.getOpcode() == ISD::BasicBlock);
199 if (Addr.getOpcode() != ISD::ADD || Addr.getNumOperands() < 2 ||
255 /*if (Addr.getOpcode() != ISD::ADD) {
290 if (Addr.getOpcode() == ISD::ADD) {
|
| /external/llvm/lib/MC/ |
| MCMachOStreamer.cpp | 181 IndirectSymbolData ISD;
182 ISD.Symbol = Symbol;
183 ISD.SectionData = getCurrentSectionData();
184 getAssembler().getIndirectSymbols().push_back(ISD);
|
| MCELFStreamer.cpp | 227 IndirectSymbolData ISD;
228 ISD.Symbol = Symbol;
229 ISD.SectionData = getCurrentSectionData();
230 getAssembler().getIndirectSymbols().push_back(ISD);
|
| /external/clang/test/CXX/temp/temp.spec/temp.expl.spec/ |
| examples.cpp | 231 namespace ISD {
233 template class BasicStringPiece<int>; // expected-error {{explicit instantiation of undefined template 'spec_vs_expl_inst::ISD::BasicStringPiece<int>'}}
|
