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/frameworks/av/media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm_gcc/
h264bsdFillRow7.S	`36 #define qTmp0 Q0.U8`
h264bsdWriteMacroblock.S	`37 #define qRow0 Q0.U8`
/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p2/src/
omxVCM4P2_PredictReconCoefIntra_s.s	`112 qPredRowBuf QN Q0.S16`
omxVCM4P2_MCReconBlock_s.s	`319 qSum6 QN Q0.U16`
/external/llvm/lib/Target/ARM/
ARMAsmPrinter.cpp	`259 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) { 260 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering"); 261 // Q registers Q0-Q15 are described by composing two D registers together. 265 unsigned QReg = Reg - ARM::Q0; [all...]`
ARMISelDAGToDAG.cpp	`[all...]`
/external/llvm/lib/Target/ARM/MCTargetDesc/
ARMMCCodeEmitter.cpp	`413 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: [all...]`
/external/v8/benchmarks/
regexp.js	`232 var s51 = computeInputVariants('NI%3Q1_CI%3Q1_PI%3Q1_EI%3Q1_HI%3Q1_HP%3Q1_IC%3Q0.0.0.0_IH%3Q0', 70); [all...]`
/external/webkit/PerformanceTests/SunSpider/tests/v8-v4/
v8-regexp.js	`185 'NI%3Q1_CI%3Q1_PI%3Q1_EI%3Q1_HI%3Q1_HP%3Q1_IC%3Q0.0.0.0_IH%3Q0'.replace(/_/g, ''); [all...]`
/external/webkit/PerformanceTests/SunSpider/tests/v8-v5/
v8-regexp.js	`185 'NI%3Q1_CI%3Q1_PI%3Q1_EI%3Q1_HI%3Q1_HP%3Q1_IC%3Q0.0.0.0_IH%3Q0'.replace(/_/g, ''); [all...]`
/external/webkit/PerformanceTests/SunSpider/tests/v8-v6/
v8-regexp.js	`185 'NI%3Q1_CI%3Q1_PI%3Q1_EI%3Q1_HI%3Q1_HP%3Q1_IC%3Q0.0.0.0_IH%3Q0'.replace(/_/g, ''); [all...]`
/external/llvm/lib/Target/ARM/Disassembler/
ARMDisassembler.cpp	`[all...]`
/external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp	`[all...]`

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