| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 88 inline SDValue getI32Imm(unsigned Imm) {
96 bool isShifterOpProfitable(const SDValue &Shift,
98 bool SelectRegShifterOperand(SDValue N, SDValue &A,
99 SDValue &B, SDValue &C,
101 bool SelectImmShifterOperand(SDValue N, SDValue &A,
102 SDValue &B, bool CheckProfitability = true);
103 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A
[all...] |
| ARMSelectionDAGInfo.cpp | 28 SDValue
30 SDValue Chain,
31 SDValue Dst, SDValue Src,
32 SDValue Size, unsigned Align,
39 return SDValue();
44 return SDValue();
47 return SDValue();
56 SDValue TFOps[MAX_LOADS_IN_LDM];
57 SDValue Loads[MAX_LOADS_IN_LDM]
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 47 bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
48 bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
52 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
54 std::vector<SDValue> &OutOps);
73 bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
74 SDValue &Base, SDValue &Offset)
[all...] |
| SparcISelLowering.cpp | 79 SDValue
80 SparcTargetLowering::LowerReturn(SDValue Chain,
83 const SmallVectorImpl<SDValue> &OutVals,
106 SDValue Flag;
127 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
135 SDValue RetAddrOffsetNode = DAG.getConstant(RetAddrOffset, MVT::i32);
147 SDValue
148 SparcTargetLowering::LowerFormalArguments(SDValue Chain,
153 SmallVectorImpl<SDValue> &InVals)
174 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.cpp | 81 SDValue Res(I, i);
96 SDValue NewVal = ReplacedValues[Res];
97 DenseMap<SDValue, SDValue>::iterator I = ReplacedValues.find(NewVal);
190 DAG.setRoot(SDValue());
332 ReplaceValueWith(SDValue(N, i), SDValue(M, i));
468 SmallVector<SDValue, 8> NewOps;
471 SDValue OrigOp = N->getOperand(i);
472 SDValue Op = OrigOp
[all...] |
| LegalizeFloatTypes.cpp | 48 SDValue R = SDValue();
104 SetSoftenedFloat(SDValue(N, ResNo), R);
107 SDValue DAGTypeLegalizer::SoftenFloatRes_BITCAST(SDNode *N) {
111 SDValue DAGTypeLegalizer::SoftenFloatRes_MERGE_VALUES(SDNode *N,
113 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
117 SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
126 SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(ConstantFPSDNode *N) {
132 SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
133 SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0))
[all...] |
| LegalizeIntegerTypes.cpp | 37 SDValue Res = SDValue();
144 SetPromotedInteger(SDValue(N, ResNo), Res);
147 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
149 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
153 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
155 SDValue Op = SExtPromotedInteger(N->getOperand(0));
160 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
162 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
167 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N)
[all...] |
| LegalizeVectorTypes.cpp | 37 SDValue R = SDValue();
122 SetScalarizedVector(SDValue(N, ResNo), R);
125 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
126 SDValue LHS = GetScalarizedVector(N->getOperand(0));
127 SDValue RHS = GetScalarizedVector(N->getOperand(1));
132 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
134 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
138 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
144 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N)
[all...] |
| LegalizeDAG.cpp | 71 SDValue OptimizeFloatStore(StoreSDNode *ST);
77 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
78 SDValue Idx, DebugLoc dl);
79 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
80 SDValue Idx, DebugLoc dl);
86 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl
[all...] |
| SelectionDAG.cpp | 135 SDValue NotZero = N->getOperand(i);
179 SDValue Zero = N->getOperand(i);
213 SDValue V = N->getOperand(i);
338 const SDValue *Ops, unsigned NumOps) {
357 const SDValue *OpList, unsigned N) {
566 Use.set(SDValue());
717 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op,
722 SDValue Ops[] = { Op };
735 SDValue Op1, SDValue Op2
[all...] |
| DAGCombiner.cpp | 100 SDValue visit(SDNode *N);
116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
125 SDValue To[] = { Res0, Res1 };
136 bool SimplifyDemandedBits(SDValue Op)
[all...] |
| LegalizeTypesGeneric.cpp | 34 SDValue &Lo, SDValue &Hi) {
35 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
39 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
42 SDValue InOp = N->getOperand(0);
100 SDValue CastInOp = DAG.getNode(ISD::BITCAST, dl, NVT, InOp);
121 SDValue StackPtr = DAG.CreateStackTemporary(InVT, Alignment);
126 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, StackPtr, PtrInfo,
148 void DAGTypeLegalizer::ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86SelectionDAGInfo.cpp | 29 SDValue
31 SDValue Chain,
32 SDValue Dst, SDValue Src,
33 SDValue Size, unsigned Align,
40 return SDValue();
49 SDValue InFlag(0, 0);
65 std::pair<SDValue,SDValue> CallResult =
76 return SDValue();
[all...] |
| X86ISelDAGToDAG.cpp | 50 /// SDValue's instead of register numbers for the leaves of the matched
59 SDValue Base_Reg;
63 SDValue IndexReg;
65 SDValue Segment;
98 void setBaseReg(SDValue Reg) {
170 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
196 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
197 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
198 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
200 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM)
[all...] |
| X86ISelLowering.cpp | 58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
59 SDValue V2);
66 static SDValue Extract128BitVector(SDValue Vec,
67 SDValue Idx,
93 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
94 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
100 return SDValue();
108 static SDValue Insert128BitVector(SDValue Result
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXSelectionDAGInfo.cpp | 28 SDValue
30 SDValue Chain,
31 SDValue Dst, SDValue Src,
32 SDValue Size, unsigned Align,
39 return SDValue();
44 return SDValue();
49 // return SDValue();
58 SDValue TFOps[MAX_LOADS_IN_LDM];
59 SDValue Loads[MAX_LOADS_IN_LDM]
[all...] |
| PTXISelLowering.cpp | 116 SDValue PTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
154 SDValue PTXTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
156 SDValue Op0 = Op.getOperand(0);
157 SDValue Op1 = Op.getOperand(1);
158 SDValue Op2 = Op.getOperand(2);
185 SDValue PTXTargetLowering::
186 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
193 SDValue targetGlobal = DAG.getTargetGlobalAddress(GV, dl, PtrVT)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 62 inline SDValue getI32Imm(unsigned Imm) {
68 inline SDValue getI64Imm(uint64_t Imm) {
73 inline SDValue getSmallIPtrImm(unsigned Imm) {
101 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl);
105 bool SelectAddrImm(SDValue N, SDValue &Disp,
106 SDValue &Base) {
113 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const
[all...] |
| PPCISelLowering.cpp | 520 static bool isFloatingPointZero(SDValue Op) {
705 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
706 SDValue OpVal(0, 0);
715 SDValue UniquedVals[4];
722 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
728 return SDValue(); // no match.
761 return SDValue();
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 166 SDValue XCoreTargetLowering::
167 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
196 SmallVectorImpl<SDValue>&Results,
212 SDValue XCoreTargetLowering::
213 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
216 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
222 SDValue XCoreTargetLowering::
223 getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
244 SDValue XCoreTargetLowering::
245 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) cons
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGISel.h | 26 class SDValue;
85 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
87 std::vector<SDValue> &OutOps) {
93 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
99 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
205 void ReplaceUses(SDValue F, SDValue T) {
212 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
227 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops)
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | 111 SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
112 SmallVector<SDValue, 16 > ShufBytes;
126 SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
127 SmallVector<SDValue, 16 > ShufBytes;
167 inline SDValue getI32Imm(uint32_t Imm) {
172 inline SDValue getSmallIPtrImm(unsigned Imm) {
193 HandleSDNode Dummy(SDValue(bvNode, 0));
208 SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
210 SDValue CGPoolOffset =
217 CurDAG->ReplaceAllUsesWith(SDValue(bvNode, 0), Dummy.getValue())
[all...] |
| SPUISelLowering.cpp | 55 SDValue
56 ExpandLibCall(RTLIB::Libcall LC, SDValue Op, SelectionDAG &DAG,
57 bool isSigned, SDValue &Hi, const SPUTargetLowering &TLI) {
61 SDValue InChain = DAG.getEntryNode();
74 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
80 std::pair<SDValue, SDValue> CallInfo =
557 static SDValue
558 LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
560 SDValue the_chain = LN->getChain()
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 51 static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
314 SDValue MultHi = ADDENode->getOperand(0);
315 SDValue MultLo = ADDCNode->getOperand(0);
342 SDValue Chain = CurDAG->getEntryNode();
348 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
355 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
357 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
362 if (!SDValue(ADDCNode, 0).use_empty())
363 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
365 if (!SDValue(ADDENode, 0).use_empty()
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 42 SDValue Reg;
106 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
107 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
108 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
111 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
112 std::vector<SDValue> &OutOps);
120 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
123 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp)
[all...] |
