| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | 496 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
|
| SelectionDAGDumper.cpp | 172 case ISD::SRL: return "srl";
|
| SelectionDAG.cpp | [all...] |
| LegalizeTypes.cpp | [all...] |
| LegalizeVectorTypes.cpp | 115 case ISD::SRL:
526 case ISD::SRL:
[all...] |
| LegalizeFloatTypes.cpp | 194 SignBit = DAG.getNode(ISD::SRL, dl, RVT, SignBit,
[all...] |
| SelectionDAGBuilder.cpp | 397 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 748 if (Shift.getOpcode() != ISD::SRL ||
762 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
763 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
773 InsertDAGNode(DAG, N, Srl);
829 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
830 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
858 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 481 case PPCISD::SRL: return "PPCISD::SRL";
[all...] |
| /external/llvm/lib/TableGen/ |
| Record.cpp | 944 case SRL: {
954 case SRL: Result = (uint64_t)LHSv >> (uint64_t)RHSv; break;
979 case SRL: Result = "!srl"; break;
[all...] |
| TGParser.cpp | 968 case tgtok::XSRL: Code = BinOpInit::SRL; Type = IntRecTy::get(); break;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 130 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
548 setTargetDAGCombine(ISD::SRL);
610 setOperationAction(ISD::SRL, MVT::i64, Custom);
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 123 case 0x41: return MBlaze::SRL;
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 450 SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
523 SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
[all...] |
| /external/v8/src/mips/ |
| assembler-mips.cc | 1298 void Assembler::srl(Register rd, Register rt, uint16_t sa) { function in class:v8::Assembler
[all...] |
| simulator-mips.cc | [all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 325 BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST);
[all...] |
| /external/llvm/include/llvm/TableGen/ |
| Record.h | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | [all...] |
