| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 162 MIB.addReg(DestReg, RegState::Define);
165 MIB.addReg(ZeroReg);
168 MIB.addReg(SrcReg, getKillRegState(KillSrc));
204 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
385 MIB.addReg(Cond[i].getReg());
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMBaseRegisterInfo.cpp | 703 .addReg(DestReg, getDefRegState(true), SubIdx)
705 .addImm(0).addImm(Pred).addReg(PredReg)
[all...] |
| Thumb2SizeReduction.cpp | 466 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| X86FloatingPoint.cpp | 250 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
259 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
842 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
[all...] |
| X86ISelLowering.cpp | [all...] |
| X86RegisterInfo.cpp | 421 .addReg(StackPtr)
432 .addReg(StackPtr).addImm(Amount);
453 .addReg(StackPtr).addImm(CalleeAmt);
|
| /external/llvm/lib/Target/Sparc/ |
| FPMover.cpp | 121 .addReg(OddSrcReg);
|
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 162 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
167 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
318 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
322 BuildMI(MBB, I, DL, get(Hexagon::TFR_64), DestReg).addReg(SrcReg);
328 DestReg).addReg(SrcReg).addReg(SrcReg);
340 Hexagon::subreg_loreg))).addReg(SrcReg);
347 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
376 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
380 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO)
[all...] |
| HexagonFrameLowering.cpp | 156 addReg(QRI->getStackRegister()).
157 addReg(HEXAGON_RESERVED_REG_1);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.cpp | 303 .addReg(tmpReg, RegState::Kill)
304 .addReg(SPU::R1);
|
| /external/llvm/lib/CodeGen/ |
| PHIElimination.cpp | 236 .addReg(IncomingReg);
320 TII->get(TargetOpcode::COPY), IncomingReg).addReg(SrcReg, 0, SrcSubReg);
|
| MachineRegisterInfo.cpp | 244 .addReg(LiveIns[i].first);
|
| MachineSSAUpdater.cpp | 192 MIB.addReg(PredValues[i].second).addMBB(PredValues[i].first);
|
| TailDuplication.cpp | 801 CopyInfos[i].first).addReg(CopyInfos[i].second));
863 .addReg(CopyInfos[i].second));
[all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| PeepholeOptimizer.cpp | 247 .addReg(DstReg, 0, SubIdx);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 71 .addReg(SrcReg)
226 .addReg(FramePtr);
|
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 208 UpdatedVRSAVE).addReg(InVRSAVE);
209 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
223 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 742 .addReg(VRI->second);
751 .addReg(I->getReg());
|
