| /external/llvm/test/CodeGen/Mips/ |
| o32_cc.ll | 51 ; CHECK: addiu $4, $zero, 12
52 ; CHECK: addiu $5, $zero, 13
53 ; CHECK: addiu $6, $zero, 14
54 ; CHECK: addiu $7, $zero, 15
67 ; CHECK: addiu $6, $zero, 23
78 ; CHECK: addiu $6, $zero, 33
79 ; CHECK: addiu $7, $zero, 24
90 ; CHECK: addiu $5, $zero, 43
91 ; CHECK: addiu $6, $zero, 34
103 ; CHECK: addiu $4, $zero, 2
[all...] |
| imm.ll | 22 ; CHECK: addiu ${{[0-9]+}}, $zero, 4660
29 ; CHECK: addiu ${{[0-9]+}}, $zero, -32204
|
| zeroreg.ll | 7 ; CHECK-NOT: addiu
17 ; CHECK-NOT: addiu
|
| tls.ll | 17 ; PIC: addiu $4, $gp, %tlsgd(t1)
23 ; STATIC: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
39 ; PIC: addiu $4, $gp, %tlsgd(t2)
44 ; STATICGP: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
47 ; STATIC: addiu $gp, $gp, %lo(__gnu_local_gp)
60 ; PIC: addiu $4, $gp, %tlsldm(f3.i)
|
| o32_cc_vararg.ll | 32 ; CHECK: addiu $sp, $sp, -16
58 ; CHECK: addiu $sp, $sp, -16
62 ; CHECK: addiu $[[R0:[0-9]+]], $sp, 20
63 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
64 ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
86 ; CHECK: addiu $sp, $sp, -16
109 ; CHECK: addiu $sp, $sp, -24
112 ; CHECK: addiu ${{[0-9]+}}, $sp, 32
137 ; CHECK: addiu $sp, $sp, -24
163 ; CHECK: addiu $sp, $sp, -2
[all...] |
| blockaddr.ll | 16 ; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($tmp[[T0]])
18 ; PIC-O32: addiu ${{[0-9]+}}, $[[R1]], %lo($tmp[[T1]])
20 ; STATIC-O32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]])
22 ; STATIC-O32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]])
24 ; PIC-N32: addiu ${{[0-9]+}}, $[[R0]], %got_ofst($tmp[[T0]])
26 ; PIC-N32: addiu ${{[0-9]+}}, $[[R1]], %got_ofst($tmp[[T1]])
28 ; STATIC-N32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]])
30 ; STATIC-N32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]])
|
| cmov.ll | 9 ; O32: addiu ${{[0-9]+}}, $gp, %got(i1)
24 ; O32: addiu $[[R1:[0-9]+]], $gp, %got(d)
25 ; O32: addiu $[[R0:[0-9]+]], $gp, %got(c)
|
| global-pointer-reg.ll | 12 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
|
| inlineasmmemop.ll | 7 ; CHECK: addiu $[[T0:[0-9]+]], $sp
|
| mips64ext.ll | 5 ; CHECK: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, 2
|
| alloca.ll | 7 ; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF:[0-9]+]]
10 ; CHECK: addiu $[[T3:[0-9]+]], $sp, [[OFF]]
41 ; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF]]
49 ; CHECK: addiu $4, $[[T1]], 40
59 ; CHECK: addiu $4, $[[T1]], 12
|
| internalfunc.ll | 10 ; CHECK: addiu $25, $[[R0]], %lo(f2)
29 ; CHECK: addiu ${{[0-9]+}}, $[[R2]], %lo(sf2)
|
| largeimmprinting.ll | 10 ; CHECK: addiu $at, $at, -24
|
| 2010-07-20-Switch.ll | 11 ; STATIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0)
14 ; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0)
|
| /external/kernel-headers/original/asm-mips/ |
| string.h | 31 "addiu\t%1,1\n\t"
34 "addiu\t%0,1\n\t"
59 "addiu\t%0,1\n\t"
61 "addiu\t%1,1\n"
82 "addiu\t%0,1\n\t"
84 "addiu\t%1,1\n\t"
116 "addiu\t%0,1\n\t"
118 "addiu\t%1,1\n"
|
| div64.h | 44 " addiu %4, %4, -1\n\t" \
46 "addiu %2, %2, 1\n" \
|
| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.cpp | 32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
56 // A single ADDiu will do if RemSize <= 16.
58 AddInstr(SeqLs, Inst(ADDiu, MaskedImm));
71 // instruction is an ADDiu or ORi. In that case, do not call GetInstSeqLsORi.
79 // Replace a ADDiu & SLL pair with a LUi.
81 // ADDiu 0x0111
86 // Check if the first two instructions are ADDiu and SLL and the shift amount
88 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) ||
92 // Sign-extend and shift operand of ADDiu and see if it still fits in 16-bit.
130 ADDiu = Mips::ADDiu
[all...] |
| MipsAnalyzeImmediate.h | 26 /// instruction in the sequence must be an ADDiu if LastInstrIsADDiu is
35 /// GetInstSeqLsADDiu - Get instrucion sequences which end with an ADDiu to
50 /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi.
58 unsigned ADDiu, ORi, SLL, LUi;
|
| MipsJITInfo.cpp | 64 "addiu $sp, $sp, -64\n"
84 "addiu $a0, $t8, -16\n"
97 "addiu $sp, $sp, 64\n"
100 "addiu $t8, $t8, -16\n"
127 // addiu $t9, $t9, %lo(NewVal)
177 // addiu t9, t9, %lo(EmittedAddr)
|
| /development/ndk/platforms/android-9/arch-mips/src/ |
| crtbegin_static.S | 126 addiu $sp,$sp,-32
134 addiu $4,$2,%lo(__EH_FRAME_BEGIN__)
136 addiu $5,$2,%lo(object.1265)
146 addiu $sp,$sp,32
166 addiu $sp,$sp,-32
195 addiu $4,$2,%lo(__EH_FRAME_BEGIN__)
214 addiu $sp,$sp,32
|
| crtbegin_so.S | 71 addiu $sp,$sp,-32
98 addiu $sp,$sp,32
|
| /bionic/libc/kernel/arch-mips/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 160 COMPARE(addiu(a0, a1, 0x0),
161 "24a40000 addiu a0, a1, 0");
162 COMPARE(addiu(s0, s1, 32767),
163 "26307fff addiu s0, s1, 32767");
164 COMPARE(addiu(t2, t3, -32768),
165 "256a8000 addiu t2, t3, -32768");
166 COMPARE(addiu(v0, v1, -1),
167 "2462ffff addiu v0, v1, -1");
|
| /prebuilts/gcc/darwin-x86/mips/mipsel-linux-android-4.4.3/sysroot/usr/include/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
