| /external/qemu/target-arm/ |
| machine.c | 23 qemu_put_be32(f, env->cp15.c0_cpuid);
24 qemu_put_be32(f, env->cp15.c0_cachetype);
25 qemu_put_be32(f, env->cp15.c0_cssel);
26 qemu_put_be32(f, env->cp15.c1_sys);
27 qemu_put_be32(f, env->cp15.c1_coproc);
28 qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
29 qemu_put_be32(f, env->cp15.c1_secfg);
30 qemu_put_be32(f, env->cp15.c1_sedbg);
31 qemu_put_be32(f, env->cp15.c1_nseac);
32 qemu_put_be32(f, env->cp15.c2_base0)
[all...] |
| helper.c | 54 env->cp15.c0_cpuid = id;
61 env->cp15.c0_cachetype = 0x1dd20d2;
62 env->cp15.c1_sys = 0x00090078;
68 env->cp15.c0_cachetype = 0x0f004006;
69 env->cp15.c1_sys = 0x00000078;
77 env->cp15.c0_cachetype = 0x1dd20d2;
78 env->cp15.c1_sys = 0x00090078;
90 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
91 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
92 env->cp15.c0_cachetype = 0x1dd20d2
[all...] |
| cpu.h | 110 /* System control coprocessor (cp15) */
157 } cp15; member in struct:CPUARMState
260 env->cp15.c13_tls2 = newtls;
380 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
410 #define ARM_CPUID(env) (env->cp15.c0_cpuid)
|
| translate.c | [all...] |
| /system/core/libpixelflinger/codeflinger/ |
| armreg.h | 108 /* Fake CPU IDs for ARMs without CP15 */
175 * Post-ARM3 CP15 registers:
210 /* CPU control register (CP15 register 1) */
230 /* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
246 #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */
247 #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */
248 #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */
|
| /external/oprofile/events/arm/armv7/ |
| events | 21 event:0x50 counters:1,2,3,4 um:zero minimum:500 name:L1_INST : Any L1 instruction cache access, excluding CP15 cache accesses
|
| /external/valgrind/main/VEX/pub/ |
| libvex_guest_arm.h | 151 Thread ID registers present in CP15 (the system control
|
| /external/qemu/hw/ |
| armv7m_nvic.c | 153 return cpu_single_env->cp15.c0_cpuid;
|
| /external/oprofile/opcontrol/ |
| opcontrol.cpp | 257 "Any L1 instruction cache access, excluding CP15 cache accesses"},
|
| /prebuilts/gcc/darwin-x86/arm/arm-linux-androideabi-4.6/lib/gcc/arm-linux-androideabi/4.6.x-google/plugin/include/config/arm/ |
| arm.h | 298 /* Nonzero if this chip implements a memory barrier via CP15. */
[all...] |
| /prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/lib/gcc/arm-eabi/4.6.x-google/plugin/include/config/arm/ |
| arm.h | 298 /* Nonzero if this chip implements a memory barrier via CP15. */
[all...] |
| /prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/lib/gcc/arm-linux-androideabi/4.6.x-google/plugin/include/config/arm/ |
| arm.h | 298 /* Nonzero if this chip implements a memory barrier via CP15. */
[all...] |
| /prebuilt/linux-x86/emulator/ |
| libqemu-audio.a | [all...] |
