| /external/qemu/target-mips/ |
| helper.h | 168 DEF_HELPER_2(ctc1, void, tl, i32)
|
| translate.c | [all...] |
| /external/v8/test/cctest/ |
| test-assembler-mips.cc | 1176 __ ctc1(zero_reg, FCSR);
1195 __ ctc1(zero_reg, FCSR); \
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/ |
| mips32.txt | 174 # CHECK: ctc1 a2,$7
|
| mips32_le.txt | 174 # CHECK: ctc1 a2,$7
|
| mips32r2.txt | 174 # CHECK: ctc1 a2,$7
|
| mips32r2_le.txt | 174 # CHECK: ctc1 a2,$7
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrFPU.td | 224 def CTC1 : FFRGPR<0x6, (outs CCR:$fs), (ins CPURegs:$rt),
225 "ctc1\t$rt, $fs", []>;
|
| MipsInstrInfo.cpp | 122 Opc = Mips::CTC1;
|
| /external/v8/src/mips/ |
| disasm-mips.cc | 479 case CTC1:
480 Format(instr, "ctc1 'rt, 'fs");
|
| constants-mips.h | 364 CTC1 = ((0 << 3) + 6) << 21,
|
| assembler-mips.cc | 1662 void Assembler::ctc1(Register rt, FPUControlRegister fs) { function in class:v8::Assembler
[all...] |
| assembler-mips.h | 803 void ctc1(Register rt, FPUControlRegister fs);
[all...] |
| macro-assembler-mips.cc | [all...] |
| simulator-mips.cc | [all...] |
| stub-cache-mips.cc | [all...] |
| /external/qemu/ |
| mips-dis.c | [all...] |
| /prebuilts/gcc/linux-x86/mips/mipsel-linux-android-4.4.3/bin/ |
| mipsel-linux-android-as | |
| mipsel-linux-android-run | |
| mipsel-linux-android-objdump | |
| /prebuilts/gcc/linux-x86/mips/mipsel-linux-android-4.4.3/mipsel-linux-android/bin/ |
| as | |
| objdump | |
| /prebuilts/gcc/darwin-x86/mips/mipsel-linux-android-4.4.3/lib/ |
| libmipsel-linux-gnu-sim.a | [all...] |
| /prebuilts/gcc/linux-x86/mips/mipsel-linux-android-4.4.3/lib/ |
| libmipsel-linux-gnu-sim.a | [all...] |
