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  /external/llvm/lib/Target/X86/InstPrinter/
X86InstComments.cpp 37 Src1Name = getRegName(MI->getOperand(0).getReg());
38 Src2Name = getRegName(MI->getOperand(2).getReg());
39 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
42 DestName = getRegName(MI->getOperand(0).getReg());
43 Src1Name = getRegName(MI->getOperand(1).getReg());
44 Src2Name = getRegName(MI->getOperand(2).getReg());
45 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
49 Src2Name = getRegName(MI->getOperand(2).getReg());
50 Src1Name = getRegName(MI->getOperand(0).getReg());
54 Src2Name = getRegName(MI->getOperand(2).getReg())
    [all...]
  /external/llvm/unittests/Support/
MDBuilderTest.cpp 37 Value *Op = MD1->getOperand(0);
51 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(0)));
52 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(1)));
53 ConstantInt *C0 = cast<ConstantInt>(R1->getOperand(0));
54 ConstantInt *C1 = cast<ConstantInt>(R1->getOperand(1));
65 EXPECT_EQ(R0->getOperand(0), R0);
66 EXPECT_EQ(R1->getOperand(0), R1);
67 EXPECT_TRUE(R0->getNumOperands() == 1 || R0->getOperand(1) == 0);
68 EXPECT_TRUE(R1->getNumOperands() == 1 || R1->getOperand(1) == 0);
76 EXPECT_TRUE(isa<MDString>(R0->getOperand(0)))
    [all...]
  /external/llvm/lib/Target/ARM/InstPrinter/
ARMInstPrinter.cpp 58 const MCOperand &Dst = MI->getOperand(0);
59 const MCOperand &MO1 = MI->getOperand(1);
60 const MCOperand &MO2 = MI->getOperand(2);
61 const MCOperand &MO3 = MI->getOperand(3);
78 const MCOperand &Dst = MI->getOperand(0);
79 const MCOperand &MO1 = MI->getOperand(1);
80 const MCOperand &MO2 = MI->getOperand(2);
102 MI->getOperand(0).getReg() == ARM::SP &&
114 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
115 MI->getOperand(3).getImm() == -4)
    [all...]
  /external/llvm/lib/Target/XCore/
XCoreISelDAGToDAG.cpp 101 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
102 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
116 Base = Addr.getOperand(0);
122 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper)
123 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
126 Base = Addr.getOperand(0).getOperand(0);
137 Base = Addr.getOperand(0);
143 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper)
144 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))
    [all...]
  /external/llvm/lib/Target/CellSPU/
SPUAsmPrinter.cpp 64 const MachineOperand &MO = MI->getOperand(OpNo);
85 unsigned int value = MI->getOperand(OpNo).getImm();
93 char value = MI->getOperand(OpNo).getImm();
103 O << (short) MI->getOperand(OpNo).getImm();
109 O << (unsigned short)MI->getOperand(OpNo).getImm();
117 const MachineOperand &MO = MI->getOperand(OpNo);
125 unsigned int value = MI->getOperand(OpNo).getImm();
133 short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
143 short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
152 assert(MI->getOperand(OpNo).isImm() &
    [all...]
  /external/llvm/lib/Target/PowerPC/InstPrinter/
PPCInstPrinter.cpp 34 unsigned char SH = MI->getOperand(2).getImm();
35 unsigned char MB = MI->getOperand(3).getImm();
36 unsigned char ME = MI->getOperand(4).getImm();
57 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
67 unsigned char SH = MI->getOperand(2).getImm();
68 unsigned char ME = MI->getOperand(3).getImm();
90 unsigned Code = MI->getOperand(OpNo).getImm();
114 char Value = MI->getOperand(OpNo).getImm();
121 unsigned char Value = MI->getOperand(OpNo).getImm()
    [all...]
  /external/llvm/lib/Transforms/InstCombine/
InstCombineVectorOps.cpp 38 isa<ConstantInt>(I->getOperand(2)))
44 (CheapToScalarize(BO->getOperand(0), isConstant) ||
45 CheapToScalarize(BO->getOperand(1), isConstant)))
49 (CheapToScalarize(CI->getOperand(0), isConstant) ||
50 CheapToScalarize(CI->getOperand(1), isConstant)))
71 if (!isa<ConstantInt>(III->getOperand(2)))
73 unsigned IIElt = cast<ConstantInt>(III->getOperand(2))->getZExtValue();
78 return III->getOperand(1);
82 return FindScalarElement(III->getOperand(0), EltNo);
86 unsigned LHSWidth = SVI->getOperand(0)->getType()->getVectorNumElements()
    [all...]
InstCombineShifts.cpp 23 assert(I.getOperand(1)->getType() == I.getOperand(0)->getType());
24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
92 if (MaskedValueIsZero(I->getOperand(0),
95 return CanEvaluateTruncated(I->getOperand(0), Ty);
112 return CanEvaluateShifted(I->getOperand(0), NumBits, isLeftShift, IC) &&
113 CanEvaluateShifted(I->getOperand(1), NumBits, isLeftShift, IC);
117 CI = dyn_cast<ConstantInt>(I->getOperand(1));
132 if (MaskedValueIsZero(I->getOperand(0)
    [all...]
InstCombineAndOrXor.cpp 135 Value *X = Op->getOperand(0);
259 Value *ShVal = Op->getOperand(0);
349 !isa<ConstantInt>(LHSI->getOperand(1))) return 0;
351 ConstantInt *N = cast<ConstantInt>(LHSI->getOperand(1));
386 return Builder->CreateSub(LHSI->getOperand(0), RHS, "fold");
387 return Builder->CreateAdd(LHSI->getOperand(0), RHS, "fold");
505 if (ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1)))
507 X = I->getOperand(0);
517 if (ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1)))
519 X = I->getOperand(0)
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonAsmPrinter.h 71 int value = MI->getOperand(OpNo).getImm();
77 int value = MI->getOperand(OpNo).getImm();
83 const MachineOperand &MO1 = MI->getOperand(OpNo);
84 const MachineOperand &MO2 = MI->getOperand(OpNo+1);
93 const MachineOperand &MO1 = MI->getOperand(OpNo);
94 const MachineOperand &MO2 = MI->getOperand(OpNo+1);
105 if (MI->getOperand(OpNo).isImm()) {
106 O << "$+" << MI->getOperand(OpNo).getImm()*4;
108 printOp(MI->getOperand(OpNo), O);
122 if (MI->getOperand(OpNo).isImm())
    [all...]
HexagonRegisterInfo.cpp 143 while (!MI.getOperand(i).isFI()) {
148 int FrameIndex = MI.getOperand(i).getIndex();
168 MI.getOperand(i).ChangeToRegister(getStackRegister(), false, false, true);
169 MI.getOperand(i+1).ChangeToImmediate(FrameSize+Offset);
188 *getSubRegisters(MI.getOperand(0).getReg()) :
189 MI.getOperand(0).getReg();
204 MI.getOperand(i).ChangeToRegister(dstReg, false, false, true);
205 MI.getOperand(i+1).ChangeToImmediate(0);
229 MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
230 MI.getOperand(i+1).ChangeToImmediate(0)
    [all...]
  /external/llvm/lib/Target/Hexagon/InstPrinter/
HexagonInstPrinter.cpp 59 const MCOperand& MO = MI->getOperand(OpNo);
74 O << MI->getOperand(OpNo).getImm();
79 O << MI->getOperand(OpNo).getImm();
84 O << MI->getOperand(OpNo).getImm();
89 O << -MI->getOperand(OpNo).getImm();
99 const MCOperand& MO0 = MI->getOperand(OpNo);
100 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
108 const MCOperand& MO0 = MI->getOperand(OpNo);
109 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
116 const MCOperand& MO = MI->getOperand(OpNo)
    [all...]
  /external/llvm/lib/MC/MCDisassembler/
EDOperand.cpp 142 result = Inst.Inst->getOperand(MCOpIndex).getImm();
146 unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg();
151 int64_t displacement = Inst.Inst->getOperand(MCOpIndex).getImm();
166 unsigned baseReg = Inst.Inst->getOperand(MCOpIndex).getReg();
167 uint64_t scaleAmount = Inst.Inst->getOperand(MCOpIndex+1).getImm();
168 unsigned indexReg = Inst.Inst->getOperand(MCOpIndex+2).getReg();
169 int64_t displacement = Inst.Inst->getOperand(MCOpIndex+3).getImm();
173 unsigned segmentReg = Inst.Inst->getOperand(MCOpIndex+4).getReg();
213 if (!Inst.Inst->getOperand(MCOpIndex).isImm())
216 result = Inst.Inst->getOperand(MCOpIndex).getImm()
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 416 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
420 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
434 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
438 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
444 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
454 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
472 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
476 GetNegatedExpression(Op.getOperand(0), DAG,
478 Op.getOperand(1));
481 GetNegatedExpression(Op.getOperand(1), DAG
    [all...]
LegalizeFloatTypes.cpp 108 return BitConvertToInteger(N->getOperand(0));
122 BitConvertToInteger(N->getOperand(0)),
123 BitConvertToInteger(N->getOperand(1)));
133 SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
136 NewOp, N->getOperand(1));
147 SDValue Op = GetSoftenedFloat(N->getOperand(0));
153 SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
154 GetSoftenedFloat(N->getOperand(1)) };
165 SDValue Op = GetSoftenedFloat(N->getOperand(0));
175 SDValue LHS = GetSoftenedFloat(N->getOperand(0))
    [all...]
LegalizeIntegerTypes.cpp 155 SDValue Op = SExtPromotedInteger(N->getOperand(0));
157 Op.getValueType(), Op, N->getOperand(1));
162 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
164 Op.getValueType(), Op, N->getOperand(1));
181 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
194 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
195 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
207 SDValue InOp = N->getOperand(0);
238 GetSplitVector(N->getOperand(0), Lo, Hi);
264 SDValue Op = GetPromotedInteger(N->getOperand(0))
    [all...]
  /external/llvm/lib/CodeGen/
ExpandPostRAPseudos.cpp 89 MachineOperand &MO = MI->getOperand(i);
98 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
99 MI->getOperand(1).isImm() &&
100 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
101 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
103 unsigned DstReg = MI->getOperand(0).getReg();
104 unsigned InsReg = MI->getOperand(2).getReg();
105 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?")
    [all...]
ProcessImplicitDefs.cpp 54 return MI->isCopy() && (!MI->getOperand(0).readsReg() ||
55 ImpDefRegs.count(MI->getOperand(0).getReg()));
57 return MI->isSubregToReg() && (!MI->getOperand(0).readsReg() ||
58 ImpDefRegs.count(MI->getOperand(0).getReg()));
66 MachineOperand &MO0 = MI->getOperand(0);
67 MachineOperand &MO1 = MI->getOperand(1);
111 if (MI->getOperand(0).readsReg())
113 unsigned Reg = MI->getOperand(0).getReg();
123 if (MI->isCopy() && MI->getOperand(0).readsReg()) {
124 MachineOperand &MO = MI->getOperand(1)
    [all...]
  /external/llvm/lib/Target/Sparc/
SparcISelDAGToDAG.cpp 85 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
88 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
92 Base = Addr.getOperand(0);
98 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
99 Base = Addr.getOperand(1);
100 Offset = Addr.getOperand(0).getOperand(0);
103 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
104 Base = Addr.getOperand(0);
105 Offset = Addr.getOperand(1).getOperand(0)
    [all...]
  /external/llvm/lib/Target/PTX/
PTXISelDAGToDAG.cpp 92 SDValue Chain = Node->getOperand(0);
93 SDValue Pred = Node->getOperand(1);
94 SDValue Target = Node->getOperand(2); // branch target
107 SDValue Chain = Node->getOperand(0);
108 SDValue Index = Node->getOperand(1);
143 SDValue Chain = Node->getOperand(0);
144 SDValue Value = Node->getOperand(1);
200 isImm(Addr.getOperand(0)) || isImm(Addr.getOperand(1)))
223 Base = Addr.getOperand(0)
    [all...]
  /external/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp 306 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
342 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
375 SDValue Op0 = N->getOperand(0);
376 SDValue Op1 = N->getOperand(1);
396 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
397 Op0.getOperand(0).getOpcode() == ISD::SRL) {
398 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
399 Op1.getOperand(0).getOpcode() != ISD::SRL) {
406 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
407 Op1.getOperand(0).getOpcode() != ISD::SRL)
    [all...]
  /external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 310 isInt32Immediate(N->getOperand(1).getNode(), Imm);
404 BaseReg = N.getOperand(0);
406 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
428 BaseReg = N.getOperand(0);
430 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
433 ShReg = N.getOperand(1);
460 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
461 Base = N.getOperand(0);
468 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
474 Base = N.getOperand(0)
    [all...]
ARMExpandPseudoInsts.cpp 78 const MachineOperand &MO = OldMI.getOperand(i);
387 bool DstIsDead = MI.getOperand(OpIdx).isDead();
388 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
400 MIB.addOperand(MI.getOperand(OpIdx++));
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
417 MIB.addOperand(MI.getOperand(OpIdx++));
418 MIB.addOperand(MI.getOperand(OpIdx++));
423 MachineOperand MO = MI.getOperand(SrcOpIdx)
    [all...]
  /external/llvm/lib/Target/MSP430/
MSP430ISelDAGToDAG.cpp 145 SDValue N0 = N.getOperand(0);
211 if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
212 !MatchAddress(N.getNode()->getOperand(1), AM))
215 if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
216 !MatchAddress(N.getNode()->getOperand(0), AM))
225 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
229 if (!MatchAddress(N.getOperand(0), AM) &&
233 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
421 Node->getOperand(0), Node->getOperand(1)
    [all...]
  /external/llvm/lib/Analysis/
PHITransAddr.cpp 35 isa<ConstantInt>(Inst->getOperand(1)))
40 // cerr << "OP:\t\t\t\t" << *PtrInst->getOperand(0);
81 if (!VerifySubExpr(I->getOperand(i), InstInputs))
138 if (Instruction *Op = dyn_cast<Instruction>(I->getOperand(i)))
179 if (Instruction *Op = dyn_cast<Instruction>(Inst->getOperand(i)))
189 Value *PHIIn = PHITranslateSubExpr(Cast->getOperand(0), CurBB, PredBB, DT);
191 if (PHIIn == Cast->getOperand(0))
219 Value *GEPOp = PHITranslateSubExpr(GEP->getOperand(i), CurBB, PredBB, DT);
222 AnyChanged |= GEPOp != GEP->getOperand(i);
248 if (GEPI->getOperand(i) != GEPOps[i])
    [all...]

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