| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/linux/ |
| phantom.h | 39 #define PHN_CONTROL 0x6 /* control byte in iaddr space */
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/linux/ |
| phantom.h | 39 #define PHN_CONTROL 0x6 /* control byte in iaddr space */
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/linux/ |
| phantom.h | 39 #define PHN_CONTROL 0x6 /* control byte in iaddr space */
|
| /system/core/toolbox/ |
| netstat.c | 38 typedef union iaddr iaddr; typedef in typeref:union:iaddr
41 union iaddr { union
101 iaddr laddr, raddr;
|
| /external/e2fsprogs/tests/progs/ |
| test_rel_cmds.ct | 68 irel_add_ref, iaddref, iaddr;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstr64Bit.td | 262 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
508 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
538 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
541 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
544 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
617 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
620 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
623 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
716 def : Pat<(zextloadi1 iaddr:$src),
717 (LBZ8 iaddr:$src)>
[all...] |
| PPCInstrInfo.td | 345 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
350 /// This is just the offset part of iaddr, used for preinc.
380 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
656 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
659 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
663 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
666 [(set GPRC:$rD, (load iaddr:$src))]>;
670 [(set F4RC:$rD, (load iaddr:$src))]>;
673 [(set F8RC:$rD, (load iaddr:$src))]>;
751 [(truncstorei8 GPRC:$rS, iaddr:$src)]>
[all...] |
| /external/valgrind/main/coregrind/m_gdbserver/ |
| m_gdbserver.c | 56 void VG_(helperc_CallDebugger) ( HWord iaddr );
872 // Check if single_stepping or if there is a break requested at iaddr.
875 void VG_(helperc_CallDebugger) ( HWord iaddr )
885 ((g = VG_(HT_lookup) (gs_addresses, (UWord)HT_addr(iaddr))) &&
887 if (iaddr == HT_addr(ignore_this_break_once)) {
[all...] |
| /external/valgrind/main/callgrind/ |
| sim.c | 62 Addr memline, iaddr; member in struct:__anon13708
165 c->loaded[i].iaddr = 0;
703 idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
720 i, idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
747 idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
762 i, idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
784 idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
799 i, idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
850 use->count, i, use->mask, loaded->memline, loaded->iaddr);
864 loaded->iaddr = CLG_(bb_base) + current_ii->instr_offset
[all...] |
| /external/tcpdump/ |
| print-isakmp.c | 99 struct sockaddr_storage iaddr; member in struct:__anon13002
197 memset(&cookiecache[ninitiator].iaddr, 0,
198 sizeof(cookiecache[ninitiator].iaddr));
202 sin = (struct sockaddr_in *)&cookiecache[ninitiator].iaddr;
217 memset(&cookiecache[ninitiator].iaddr, 0,
218 sizeof(cookiecache[ninitiator].iaddr));
223 sin6 = (struct sockaddr_in6 *)&cookiecache[ninitiator].iaddr;
287 if (sa->sa_family != ((struct sockaddr *)&cookiecache[i].iaddr)->sa_family)
301 if (memcmp(&ss, &cookiecache[i].iaddr, salen) == 0)
[all...] |
| /external/valgrind/main/lackey/ |
| lk_main.c | 511 static void addEvent_Ir ( IRSB* sb, IRAtom* iaddr, UInt isize )
522 evt->addr = iaddr;
614 Addr iaddr = 0, dst; local
679 iaddr = st->Ist.IMark.addr;
847 tl_assert(iaddr != 0);
850 condition_inverted = (dst == iaddr + ilen);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.td | 138 def iaddr : ComplexPattern<i32, 2, "SelectAddrRegImm", [frameindex], []>;
259 [(set (i32 GPR:$dst), (OpNode iaddr:$addr))], IIC_MEMl>;
271 [(OpNode (i32 GPR:$dst), iaddr:$addr)], IIC_MEMs>;
[all...] |
| MBlazeInstrFPU.td | 29 [(set (f32 GPR:$dst), (OpNode iaddr:$addr))], IIC_MEMl>;
39 [(OpNode (f32 GPR:$dst), iaddr:$addr)], IIC_MEMs>;
|
| /external/valgrind/main/cachegrind/ |
| cg_main.c | 319 //VG_(printf)("1I_0D : CCaddr=0x%010lx, iaddr=0x%010lx, isize=%lu\n",
364 //VG_(printf)("1I_1Dr: CCaddr=0x%010lx, iaddr=0x%010lx, isize=%lu\n"
379 //VG_(printf)("1I_1Dw: CCaddr=0x%010lx, iaddr=0x%010lx, isize=%lu\n"
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrInfo.td | 149 [(set VECREG:$rT, (load iaddr:$disp))]>;
258 [(store VECREG:$rT, iaddr:$disp)]>;
[all...] |
