| /external/llvm/test/CodeGen/Mips/ |
| o32_cc.ll | 7 ; CHECK: ldc1 $f12, %lo
8 ; CHECK: ldc1 $f14, %lo
30 ; CHECK: ldc1 $f14, %lo
40 ; CHECK: ldc1 $f12, %lo
66 ; CHECK: ldc1 $f12, %lo
77 ; CHECK: ldc1 $f12, %lo
180 ; CHECK: ldc1 $f12, %lo
283 ; CHECK: ldc1 $f12, %lo
296 ; CHECK: ldc1 $f12, %lo
|
| mips64fpldst.ll | 25 ; CHECK-N64: ldc1 $f{{[0-9]+}}, 0($[[R0]])
28 ; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]])
|
| o32_cc_vararg.ll | 66 ; CHECK: ldc1 $f0, 0($[[R3]])
113 ; CHECK: ldc1 $f0, 32($sp)
169 ; CHECK: ldc1 $f0, 0($[[R3]])
216 ; CHECK: ldc1 $f0, 48($sp)
270 ; CHECK: ldc1 $f0, 0($[[R3]])
|
| o32_cc_byval.ll | 50 ; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp)
|
| /external/v8/test/cctest/ |
| test-assembler-mips.cc | 290 __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
291 __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
363 __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
364 __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
425 __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
426 __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
572 __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
573 __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
786 __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, a)));
1178 __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, round_up_in)));
[all...] |
| /external/v8/src/mips/ |
| lithium-gap-resolver-mips.cc | 177 __ ldc1(kLithiumScratchDouble, cgen_->ToMemOperand(source));
286 __ ldc1(cgen_->ToDoubleRegister(destination), source_operand);
302 __ ldc1(kLithiumScratchDouble, source_operand);
|
| constants-mips.cc | 336 case LDC1:
|
| code-stubs-mips.cc | 598 // kValueOffset. On MIPS this workaround is built into ldc1 so there's no
600 __ ldc1(dst, FieldMemOperand(object, HeapNumber::kValueOffset));
795 __ ldc1(double_dst, FieldMemOperand(object, HeapNumber::kValueOffset));
867 __ ldc1(double_scratch, FieldMemOperand(object, HeapNumber::kValueOffset));
[all...] |
| disasm-mips.cc | 910 case LDC1:
911 Format(instr, "ldc1 'ft, 'imm16s('rs)");
|
| lithium-codegen-mips.cc | 348 __ ldc1(dbl_scratch, mem_op);
[all...] |
| constants-mips.h | 295 LDC1 = ((6 << 3) + 5) << kOpcodeShift,
|
| macro-assembler-mips.cc | 132 ldc1(reg, MemOperand(sp, i * kDoubleSize));
890 ldc1(FPURegister::from_code(i), MemOperand(sp, stack_offset));
904 ldc1(FPURegister::from_code(i), MemOperand(sp, stack_offset));
[all...] |
| assembler-mips.h | 795 void ldc1(FPURegister fd, const MemOperand& src);
[all...] |
| deoptimizer-mips.cc | [all...] |
| simulator-mips.cc | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsJITInfo.cpp | 95 "ldc1 $f12, 48($sp)\n"
96 "ldc1 $f14, 56($sp)\n"
|
| MipsInstrFPU.td | 255 def LDC164_P8 : FPLoad<0x35, "ldc1", FGR64, mem64> {
269 def LDC164 : FPLoad<0x35, "ldc1", FGR64, mem>;
274 def LDC1 : FPLoad<0x35, "ldc1", AFGR64, mem>;
|
| MipsInstrInfo.cpp | 55 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
226 Opc = Mips::LDC1;
|
| /external/webkit/Source/JavaScriptCore/assembler/ |
| MacroAssemblerMIPS.h | [all...] |
| MIPSAssembler.h | 546 void ldc1(FPRegisterID ft, RegisterID rs, int offset) function in class:JSC::MIPSAssembler
|
| /external/llvm/test/MC/Disassembler/Mips/ |
| mips32.txt | 225 # CHECK: ldc1 $f9,9158(a3)
|
| mips32_le.txt | 225 # CHECK: ldc1 $f9,9158(a3)
|
| mips32r2.txt | 228 # CHECK: ldc1 $f9,9158(a3)
|
| mips32r2_le.txt | 228 # CHECK: ldc1 $f9,9158(a3)
|
| /external/v8/src/ |
| deoptimizer.h | 380 // Prevent gcc from using load-double (mips ldc1) on (possibly)
|
