/external/llvm/test/TableGen/ |
Tree.td | 6 class RegisterClass; 11 def R32 : RegisterClass;
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TreeNames.td | 6 class RegisterClass; 11 def R32 : RegisterClass;
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TargetInstrSpec.td | 37 class RegisterClass<list<ValueType> regTypes, list<Register> regList> { 59 def VR128 : RegisterClass<[v2i64, v2f64], 65 def REGCLASS : RegisterClass<[], []>;
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MultiPat.td | 45 class RegisterClass<list<ValueType> regTypes, list<Register> regList> { 67 def VR128 : RegisterClass<[v2i64, v2f64], 73 def REGCLASS : RegisterClass<[], []>;
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Slice.td | 36 class RegisterClass<list<ValueType> regTypes, list<Register> regList> { 58 def FR32 : RegisterClass<[f32],
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cast.td | 36 class RegisterClass<list<ValueType> regTypes, list<Register> regList> { 58 def VR128 : RegisterClass<[v2i64, v2f64],
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TargetInstrInfo.td | 11 class RegisterClass; 35 def R8 : RegisterClass; 36 def R16 : RegisterClass; 37 def R32 : RegisterClass;
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/external/jmonkeyengine/engine/src/networking/com/jme3/network/serializing/ |
Serializer.java | 100 registerClass(boolean.class, new BooleanSerializer()); 101 registerClass(byte.class, new ByteSerializer()); 102 registerClass(char.class, new CharSerializer()); 103 registerClass(short.class, new ShortSerializer()); 104 registerClass(int.class, new IntSerializer()); 105 registerClass(long.class, new LongSerializer()); 106 registerClass(float.class, new FloatSerializer()); 107 registerClass(double.class, new DoubleSerializer()); 109 registerClass(Boolean.class, new BooleanSerializer()); 110 registerClass(Byte.class, new ByteSerializer()) [all...] |
/external/llvm/lib/Target/X86/ |
X86RegisterInfo.td | 288 def GR8 : RegisterClass<"X86", [i8], 8, 297 def GR16 : RegisterClass<"X86", [i16], 16, 303 def GR32 : RegisterClass<"X86", [i32], 32, 312 def GR64 : RegisterClass<"X86", [i64], 64, 323 def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>; 326 def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 7)>; 329 def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>; 337 def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>; 338 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>; 339 def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)> [all...] |
/external/llvm/lib/Target/Mips/ |
MipsCondMov.td | 19 class CondMovIntInt<RegisterClass CRC, RegisterClass DRC, bits<6> funct, 28 class CondMovIntFP<RegisterClass CRC, RegisterClass DRC, bits<5> fmt, 38 class CondMovFPInt<RegisterClass RC, SDNode cmov, bits<1> tf, 49 class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf, 60 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC, 78 multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC [all...] |
MipsInstrInfo.td | 312 InstrItinClass itin, RegisterClass RC, bit isComm = 0>: 322 InstrItinClass itin, RegisterClass RC, bit isComm = 0>: 331 Operand Od, PatLeaf imm_type, RegisterClass RC> : 339 Operand Od, PatLeaf imm_type, RegisterClass RC> : 355 class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>: 366 RegisterClass RC>: 379 SDNode OpNode, RegisterClass RC>: 387 class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>: 405 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 413 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC [all...] |
MipsRegisterInfo.td | 248 def CPURegs : RegisterClass<"Mips", [i32], 32, (add 258 def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add 277 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 279 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add 289 def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)> { 294 def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31)>; 297 def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>; 298 def HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)> { 303 def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>; 304 def HWRegs64 : RegisterClass<"Mips", [i64], 32, (add HWR29_64)> [all...] |
/external/llvm/lib/Target/ARM/ |
ARMRegisterInfo.td | 184 def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), 200 def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> { 212 def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)>; 218 def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> { 227 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>; 230 def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>; 236 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R9, R12)> { 244 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> { 250 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)>; 254 def SPR_8 : RegisterClass<"ARM", [f32], 32, (trunc SPR, 16)> [all...] |
/external/llvm/lib/Target/PTX/ |
PTXRegisterInfo.td | 30 def RegPred : RegisterClass<"PTX", [i1], 8, (add DUMMY_REG)>; 31 def RegI16 : RegisterClass<"PTX", [i16], 16, (add DUMMY_REG)>; 32 def RegI32 : RegisterClass<"PTX", [i32], 32, (add DUMMY_REG)>; 33 def RegI64 : RegisterClass<"PTX", [i64], 64, (add DUMMY_REG)>; 34 def RegF32 : RegisterClass<"PTX", [f32], 32, (add DUMMY_REG)>; 35 def RegF64 : RegisterClass<"PTX", [f64], 64, (add DUMMY_REG)>;
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/external/jmonkeyengine/engine/src/test/jme3test/network/ |
TestMessages.java | 68 Serializer.registerClass(PingMessage.class); 69 Serializer.registerClass(PongMessage.class);
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TestSerialization.java | 143 Serializer.registerClass(SomeObject.class); 144 Serializer.registerClass(TestSerializationMessage.class);
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/external/llvm/lib/Target/CellSPU/ |
SPURegisterInfo.td | 159 def GPRC : RegisterClass<"SPU", [i128], 128, 164 def R64C : RegisterClass<"SPU", [i64], 128, (add GPRC)>; 167 def R64FP : RegisterClass<"SPU", [f64], 128, (add GPRC)>; 170 def R32C : RegisterClass<"SPU", [i32], 128, (add GPRC)>; 173 def R32FP : RegisterClass<"SPU", [f32], 128, (add GPRC)>; 176 def R16C : RegisterClass<"SPU", [i16], 128, (add GPRC)>; 179 def R8C : RegisterClass<"SPU", [i8], 128, (add GPRC)>; 182 def VECREG : RegisterClass<"SPU", [v16i8,v8i16,v4i32,v4f32,v2i64,v2f64], 128,
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/external/llvm/lib/Target/PowerPC/ |
PPCRegisterInfo.td | 279 def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12), 283 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12), 294 def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13), 296 def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>; 298 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128, 303 def CRBITRC : RegisterClass<"PPC", [i32], 32, 316 def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6, 321 def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)>; 322 def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)>; 323 def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)> [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreRegisterInfo.td | 45 def GRRegs : RegisterClass<"XCore", [i32], 32, 54 def RRegs : RegisterClass<"XCore", [i32], 32, (add CP, DP, SP, LR)> {
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/external/chromium/base/win/ |
wrapped_window_proc_unittest.cc | 64 RegisterClass(&wc);
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/external/llvm/lib/Target/Hexagon/ |
HexagonRegisterInfo.td | 143 def IntRegs : RegisterClass<"Hexagon", [i32], 32, 151 def DoubleRegs : RegisterClass<"Hexagon", [i64], 64, 158 def PredRegs : RegisterClass<"Hexagon", [i1], 32, (add (sequence "P%u", 0, 3))> 163 def CRRegs : RegisterClass<"Hexagon", [i32], 32,
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/sdk/emulator/opengl/host/libs/libOpenglRender/ |
NativeWindowsSubWindow.cpp | 39 RegisterClass(&wc);
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/external/llvm/lib/Target/MBlaze/ |
MBlazeRegisterInfo.td | 112 def GPR : RegisterClass<"MBlaze", [i32,f32], 32, (sequence "R%u", 0, 31)>; 114 def SPR : RegisterClass<"MBlaze", [i32], 32, (add 146 def CRC : RegisterClass<"MBlaze", [i32], 32, (add CARRY)> {
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/external/llvm/lib/Target/Sparc/ |
SparcRegisterInfo.td | 143 def IntRegs : RegisterClass<"SP", [i32], 32, 158 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>; 160 def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 15)>;
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/external/llvm/utils/TableGen/ |
RegisterInfoEmitter.h | 12 // RegisterAliases, and RegisterClass classes to gather this information.
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