Lines Matching refs:x02
41 #define SA_ADDR0 0x02
56 #define EDLC_RSTAT (ioaddr + 0x02) /* EDLC receive csr */
57 #define EDLC_RCLR (ioaddr + 0x02) /* EDLC receive "Clear IRQ" */
85 #define XS_16COLL 0x02 /* 16th collision occurred */
90 #define XS_CLR_16COLL 0x02 /* clear 16th collision */
98 #define XM_COLL16 0x02 /* =1 to enable Xmt 16th Coll ints */
108 #define RS_CRC_ERR 0x02 /* Bad CRC on rcvd pkt */
117 #define RS_CLR_CRC_ERR 0x02 /* clear CRC error */
125 #define RM_CRC_ERR 0x02 /* =1 to enable Bad CRC error ints */
135 #define RMD_MULTICAST 0x02 /* receive multicasts too. unusual */
143 #define XMD_LBC 0x02 /* =1 for loopback. normally set */
164 #define IS_R_INT 0x02 /* =0 iff unmasked Rcv interrupt */
