Lines Matching full:live
17 // Register live intervals: Registers must be defined only once, and must be
100 // Vregs that must be live in because they are used without being
108 // Regs defined in MBB and live out. Note that vregs passing through may
109 // be live out without being mentioned here.
169 // Live-out registers are either in regsLiveOut or vregsPassed.
414 // If this block has allocatable physical registers live-in, check that
422 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
553 report("MBB live-in list contains non-physical register", MBB);
742 *OS << "Live stack: " << LI << '\n';
746 *OS << "Live stack: " << LI << '\n';
795 report("No live range at use", MO, MONum);
796 *OS << UseIdx << " is not live in " << LI << '\n';
801 report("Live range continues after kill flag", MO, MONum);
802 *OS << "Live range: " << LI << '\n';
805 report("Virtual register has no Live interval", MO, MONum);
817 // We don't know which virtual registers are live in, so only complain
819 // must be live in. PHI instructions are handled separately.
841 // Check LiveInts for a live range, but only for virtual registers.
855 report("No live range at def", MO, MONum);
856 *OS << DefIdx << " is not live in " << LI << '\n';
859 report("Virtual register has no Live interval", MO, MONum);
907 // can pass through an MBB live, but may not be live every time. It is assumed
910 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
948 // First push live-in regs to predecessors' vregsRequired.
995 report("PHI operand is not live-out from predecessor",
1057 << " must be live through the block.\n";
1063 << " is not needed live through the block.\n";
1094 report("Valno not live at def and not marked unused", MF);
1104 report("Live range at def has different valno", MF);
1106 << " where valno #" << DefVNI->id << " is live in " << LI << '\n';
1177 assert(VNI && "Live range has no valno");
1180 report("Foreign valno in live range", MF);
1186 report("Live range valno is marked unused", MF);
1193 report("Bad start of live segment, no basic block", MF);
1200 report("Live segment must begin at MBB entry or valno def", MBB);
1209 report("Bad end of live segment, no basic block", MF);
1215 // No more checks for live-out segments.
1219 // The live segment is ending inside EndMBB
1223 report("Live segment doesn't end at a valid instruction", EndMBB);
1232 report("Live segment ends at B slot of an instruction", MI);
1241 report("Live segment ending at dead slot spans instructions", MI);
1247 // A live segment can only end at an early-clobber slot if it is being
1251 report("Live segment ending at early clobber slot must be "
1261 // A live range can end with either a redefinition, a kill flag on a
1282 report("Instruction ending live range doesn't read the register",
1290 // Now check all the basic blocks in this live segment.
1292 // Is this live range the beginning of a non-PHIDef VN?
1294 // Not live-in to any blocks.
1310 // Check that VNI is live-out of all predecessors.
1320 report("Register not marked live out of predecessor", *PI);
1321 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1322 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
1328 report("Different value live out of predecessor", *PI);
1329 *OS << "Valno #" << PVNI->id << " live out of BB#"
1331 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1346 report("Multiple connected components in live interval", MF);
