Lines Matching refs:getSUnit
192 Topo.AddPred(SU, D.getSUnit());
200 Topo.RemovePred(SU, D.getSUnit());
345 SUnit *PredSU = PredEdge->getSUnit();
515 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) &&
517 LiveRegDefs[I->getReg()] = I->getSUnit();
767 SUnit *PredSU = PredEdge->getSUnit();
789 assert(LiveRegDefs[I->getReg()] == I->getSUnit() &&
833 I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight())
834 LiveRegGens[I->getReg()] = I->getSUnit();
1002 else if (isOperandOf(I->getSUnit(), LoadNode))
1035 SUnit *SuccDep = D.getSUnit();
1047 SUnit *SuccDep = D.getSUnit();
1089 SUnit *SuccSU = I->getSUnit();
1129 SUnit *SuccSU = I->getSUnit();
1241 CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs,
1813 SUnit *PredSU = I->getSUnit();
1914 SUnit *PredSU = I->getSUnit();
1964 SUnit *PredSU = I->getSUnit();
2008 SUnit *PredSU = I->getSUnit();
2090 SUnit *PredSU = I->getSUnit();
2158 unsigned Height = I->getSUnit()->getHeight();
2161 if (I->getSUnit()->getNode() &&
2162 I->getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)
2163 Height = closestSucc(I->getSUnit())+1;
2189 const SUnit *PredSU = I->getSUnit();
2212 const SUnit *SuccSU = I->getSUnit();
2250 I->getSUnit()->isVRegCycle = true;
2263 SUnit *PredSU = I->getSUnit();
2267 I->getSUnit()->isVRegCycle = 0;
2282 if (I->getSUnit()->isVRegCycle &&
2283 I->getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {
2682 SUnit *SuccSU = SI->getSUnit();
2689 scheduleDAG->IsReachable(DepSU, PI->getSUnit()))
2698 scheduleDAG->IsReachable(DepSU, PI->getSUnit()))
2800 PredSU = II->getSUnit();
2823 SUnit *PredSuccSU = II->getSUnit();
2846 SUnit *SuccSU = Edge.getSUnit();
2893 SUnit *SuccSU = I->getSUnit();
2909 SuccSU = SuccSU->Succs.front().getSUnit();
