Lines Matching refs:Regs
573 /// Regs - This list holds the registers assigned to the values.
577 SmallVector<unsigned, 4> Regs;
581 RegsForValue(const SmallVector<unsigned, 4> ®s,
583 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
594 Regs.push_back(Reg + i);
614 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
669 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
671 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
680 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
685 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
742 unsigned NumRegs = Regs.size();
759 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
761 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
793 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
796 else if (!Regs.empty() &&
797 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
804 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
815 assert(Reg < Regs.size() && "Mismatch in # registers expected");
816 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
5761 SmallVector<unsigned, 4> Regs;
5816 Regs.push_back(AssignedReg);
5818 // If this is an expanded reference, add the rest of the regs to Regs.
5828 Regs.push_back(*I);
5832 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5846 Regs.push_back(RegInfo.createVirtualRegister(RC));
5848 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6061 // appropriate registers and processing the output regs.
6089 if (OpInfo.AssignedRegs.Regs.empty()) {
6161 MatchedRegs.Regs.push_back
6232 if (OpInfo.AssignedRegs.Regs.empty()) {
6250 if (!OpInfo.AssignedRegs.Regs.empty())
6270 if (!RetValRegs.Regs.empty()) {
