Lines Matching refs:NumAlignedDPRCS2Regs
36 unsigned NumAlignedDPRCS2Regs);
570 unsigned NumAlignedDPRCS2Regs,
587 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
639 unsigned NumAlignedDPRCS2Regs) const {
658 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
713 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
718 unsigned NumAlignedDPRCS2Regs,
765 .addImm(8 * NumAlignedDPRCS2Regs)));
785 // Now spill NumAlignedDPRCS2Regs registers starting from d8.
791 if (NumAlignedDPRCS2Regs >= 6) {
801 NumAlignedDPRCS2Regs -= 4;
809 if (NumAlignedDPRCS2Regs >= 4) {
817 NumAlignedDPRCS2Regs -= 4;
821 if (NumAlignedDPRCS2Regs >= 2) {
828 NumAlignedDPRCS2Regs -= 2;
832 if (NumAlignedDPRCS2Regs) {
848 unsigned NumAlignedDPRCS2Regs) {
856 switch(NumAlignedDPRCS2Regs) {
872 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
877 unsigned NumAlignedDPRCS2Regs,
905 // Now restore NumAlignedDPRCS2Regs registers starting from d8.
909 if (NumAlignedDPRCS2Regs >= 6) {
917 NumAlignedDPRCS2Regs -= 4;
925 if (NumAlignedDPRCS2Regs >= 4) {
932 NumAlignedDPRCS2Regs -= 4;
936 if (NumAlignedDPRCS2Regs >= 2) {
942 NumAlignedDPRCS2Regs -= 2;
946 if (NumAlignedDPRCS2Regs)
968 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
974 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
979 if (NumAlignedDPRCS2Regs)
980 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
995 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
999 if (NumAlignedDPRCS2Regs)
1000 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1006 NumAlignedDPRCS2Regs);
