Lines Matching refs:Regs
578 SmallVector<std::pair<unsigned,bool>, 4> Regs;
610 Regs.push_back(std::make_pair(Reg, isKill));
613 if (Regs.empty())
615 if (Regs.size() > 1 || StrOpc== 0) {
619 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
620 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
621 } else if (Regs.size() == 1) {
624 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
629 Regs.clear();
648 SmallVector<unsigned, 4> Regs;
675 Regs.push_back(Reg);
678 if (Regs.empty())
680 if (Regs.size() > 1 || LdrOpc == 0) {
684 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
685 MIB.addReg(Regs[i], getDefRegState(true));
691 } else if (Regs.size() == 1) {
694 if (Regs[0] == ARM::PC)
695 Regs[0] = ARM::LR;
697 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
709 Regs.clear();
789 // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
808 // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
820 regs.
908 // 16-byte aligned vld1.64 with 4 d-regs and writeback.
924 // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
935 // 16-byte aligned vld1.64 with 2 d-regs.
