Lines Matching defs:Const
76 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,
88 static const uint16_t GPRArgRegs[] = {
840 std::pair<const TargetRegisterClass*, uint8_t>
841 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
842 const TargetRegisterClass *RRC = 0;
877 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1017 EVT ARMTargetLowering::getSetCCResultType(EVT VT) const {
1024 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
1039 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
1045 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
1049 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1067 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1068 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1139 bool isVarArg) const {
1177 const SmallVectorImpl<ISD::InputArg> &Ins,
1179 SmallVectorImpl<SDValue> &InVals) const {
1250 const CCValAssign &VA,
1251 ISD::ArgFlagsTy Flags) const {
1266 ISD::ArgFlagsTy Flags) const {
1292 const SmallVectorImpl<ISD::OutputArg> &Outs,
1293 const SmallVectorImpl<SDValue> &OutVals,
1294 const SmallVectorImpl<ISD::InputArg> &Ins,
1296 SmallVectorImpl<SDValue> &InVals) const {
1406 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1407 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1491 const GlobalValue *GV = G->getGlobal();
1505 const char *Sym = S->getSymbol();
1521 const GlobalValue *GV = G->getGlobal();
1557 const char *Sym = S->getSymbol();
1614 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1615 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
1646 ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const {
1675 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1676 const TargetInstrInfo *TII) {
1723 const SmallVectorImpl<ISD::OutputArg> &Outs,
1724 const SmallVectorImpl<SDValue> &OutVals,
1725 const SmallVectorImpl<ISD::InputArg> &Ins,
1726 SelectionDAG& DAG) const {
1727 const Function *CallerF = DAG.getMachineFunction().getFunction();
1810 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1811 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1851 const SmallVectorImpl<ISD::OutputArg> &Outs,
1852 const
1853 DebugLoc dl, SelectionDAG &DAG) const {
1939 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2003 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2034 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2039 SelectionDAG &DAG) const {
2045 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2071 SelectionDAG &DAG) const {
2111 SelectionDAG &DAG) const {
2112 const GlobalValue *GV = GA->getGlobal();
2160 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2174 SelectionDAG &DAG) const {
2177 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2218 SelectionDAG &DAG) const {
2221 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2279 SelectionDAG &DAG) const {
2301 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2310 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2318 const ARMSubtarget *Subtarget) const {
2364 const ARMSubtarget *Subtarget) {
2393 const ARMSubtarget *Subtarget) {
2411 const ARMSubtarget *Subtarget) {
2446 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2454 DebugLoc dl) const {
2458 const TargetRegisterClass *RC;
2489 const {
2516 unsigned ArgOffset) const {
2544 const TargetRegisterClass *RC;
2571 const SmallVectorImpl<ISD::InputArg>
2575 const {
2627 const TargetRegisterClass *RC;
2727 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2739 DebugLoc dl) const {
2797 DebugLoc dl) const {
2809 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2827 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2839 const ConstantSDNode *CMOVTrue =
2841 const ConstantSDNode *CMOVFalse =
2879 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2916 const ARMSubtarget *Subtarget) {
2983 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3033 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3076 const {
3209 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3291 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3312 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3385 SelectionDAG &DAG) const {
3421 SelectionDAG &DAG) const {
3453 SelectionDAG &DAG) const {
3471 const ARMSubtarget *ST) {
3483 const ARMSubtarget *ST) {
3518 const ARMSubtarget *ST) {
3823 const ARMSubtarget *ST) const {
4077 const ARMSubtarget *ST, DebugLoc dl) {
4096 const ARMSubtarget *ST) const {
4223 SelectionDAG &DAG) const {
4363 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4364 EVT VT) const {
4793 const APInt &CInt = C->getAPIntValue();
5136 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5197 SelectionDAG &DAG) const {
5245 unsigned Size) const {
5250 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5283 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5348 unsigned Size, unsigned BinOpcode) const {
5350 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5352 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5397 const TargetRegisterClass *TRC =
5455 ARMCC::CondCodes Cond) const {
5456 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5458 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5507 const TargetRegisterClass *TRC =
5570 bool NeedsCarry, bool IsCmpxchg) const {
5572 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5574 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5617 const TargetRegisterClass *TRC =
5707 MachineBasicBlock *DispatchBB, int FI) const {
5708 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5714 const Function *F = MF->getFunction();
5725 const TargetRegisterClass *TRC =
5821 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
5822 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5830 const TargetRegisterClass *TRC =
5985 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6074 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6136 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6137 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6138 const uint16_t *SavedRegs = RI.getCalleeSavedRegs(MF);
6219 MachineBasicBlock *BB) const {
6220 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6388 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6505 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6574 SDNode *Node) const {
6581 const MCInstrDesc *MCID = &MI->getDesc();
6592 const ARMBaseInstrInfo *TII =
6593 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo());
6618 const MachineOperand &MO = MI->getOperand(i);
6653 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6713 const ARMSubtarget *Subtarget) {
6772 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6804 const ARMSubtarget *Subtarget){
6823 const ARMSubtarget *Subtarget) {
6862 const ARMSubtarget *Subtarget) {
6890 const ARMSubtarget *Subtarget) {
7017 const ARMSubtarget *Subtarget) {
7061 const ARMSubtarget *Subtarget) {
7248 const ARMSubtarget *Subtarget) {
7363 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7587 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7896 const ARMSubtarget *Subtarget) {
7932 const ARMSubtarget *Subtarget) {
8172 const ARMSubtarget *ST) {
8188 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8219 const ARMSubtarget *ST) {
8231 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8259 const ARMSubtarget *ST) {
8343 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
8406 DAGCombinerInfo &DCI) const {
8465 EVT VT) const {
8469 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
8494 MachineFunction &MF) const {
8495 const Function *F = MF.getFunction();
8547 const ARMSubtarget *Subtarget) {
8580 const ARMSubtarget *Subtarget) {
8616 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
8617 EVT VT) const {
8651 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8652 Type *Ty) const {
8714 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
8728 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
8823 SelectionDAG &DAG) const {
8862 SelectionDAG &DAG) const {
8906 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8909 const SelectionDAG &DAG,
8910 unsigned Depth) const {
8932 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
8966 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
8995 AsmOperandInfo &info, const char *constraint) const {
9024 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
9026 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9027 EVT VT) const {
9075 SelectionDAG &DAG) const {
9238 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9261 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
9275 const CallInst &I,
9276 unsigned Intrinsic) const {
