Lines Matching full:v2i64
403 addRegisterClass(MVT::v2i64, SPU::VECREGRegisterClass);
450 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
1106 SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T);
1177 v2i64:
1326 case MVT::v2i64:
1694 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T));
1717 case MVT::v2i64: {
1866 maskVT = MVT::v2i64;
1971 case MVT::v2i64: n_copies = 2; VT = MVT::i64; break;
2746 MVT mvt = Op0VT == MVT::i64 ? MVT::v2i64 : MVT::v4i32;
