Lines Matching defs:Const
58 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
444 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
445 const TargetMachine &TM = getTargetMachine();
462 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
511 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
526 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
842 SelectionDAG &DAG) const {
886 SelectionDAG &DAG) const {
971 SelectionDAG &DAG) const {
999 SelectionDAG &DAG) const {
1086 SelectionDAG &DAG) const {
1138 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1139 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1187 SelectionDAG &DAG) const {
1190 const Constant *C = CP->getConstVal();
1201 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1213 SelectionDAG &DAG) const {
1216 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1226 SelectionDAG &DAG) const {
1230 const GlobalValue *GV = GSDN->getGlobal();
1258 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1302 const PPCSubtarget &Subtarget) const {
1308 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1410 SelectionDAG &DAG) const {
1415 SelectionDAG &DAG) const {
1455 const PPCSubtarget &Subtarget) const {
1466 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1517 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1565 static const uint16_t ArgRegs[] = {
1569 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1592 static const uint16_t ArgRegs[] = {
1597 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1616 static const uint16_t *GetFPR() {
1617 static const uint16_t FPR[] = {
1640 const SmallVectorImpl<ISD::InputArg>
1644 const {
1658 const SmallVectorImpl<ISD::InputArg>
1661 SmallVectorImpl<SDValue> &InVals) const {
1717 const TargetRegisterClass *RC;
1798 static const uint16_t GPArgRegs[] = {
1802 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1804 static const uint16_t FPArgRegs[] = {
1808 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1876 const SmallVectorImpl<ISD::InputArg>
1879 SmallVectorImpl<SDValue> &InVals) const {
1897 static const uint16_t GPR_32[] = { // 32-bit registers.
1901 static const uint16_t GPR_64[] = { // 64-bit registers.
1906 static const uint16_t *FPR = GetFPR();
1908 static const uint16_t VR[] = {
1913 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1914 const unsigned Num_FPR_Regs = 13;
1915 const unsigned Num_VR_Regs = array_lengthof( VR);
1919 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2244 const SmallVectorImpl<ISD::OutputArg>
2246 const SmallVectorImpl<SDValue> &OutVals,
2329 const SmallVectorImpl<ISD::InputArg> &Ins,
2330 SelectionDAG& DAG) const {
2392 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2473 DebugLoc dl) const {
2570 const PPCSubtarget &PPCSubTarget) {
2740 const SmallVectorImpl<ISD::InputArg> &Ins,
2742 SmallVectorImpl<SDValue> &InVals) const {
2772 const SmallVectorImpl<ISD::InputArg> &Ins,
2773 SmallVectorImpl<SDValue> &InVals) const {
2788 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2789 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2870 const SmallVectorImpl<ISD::OutputArg> &Outs,
2871 const SmallVectorImpl<SDValue> &OutVals,
2872 const SmallVectorImpl<ISD::InputArg> &Ins,
2874 SmallVectorImpl<SDValue> &InVals) const {
2893 const SmallVectorImpl<ISD::OutputArg> &Outs,
2894 const SmallVectorImpl<SDValue> &OutVals,
2895 const SmallVectorImpl<ISD::InputArg> &Ins,
2897 SmallVectorImpl<SDValue> &InVals) const {
3102 const SmallVectorImpl<ISD::OutputArg> &Outs,
3103 const SmallVectorImpl<SDValue> &OutVals,
3104 const SmallVectorImpl<ISD::InputArg> &Ins,
3106 SmallVectorImpl<SDValue> &InVals) const {
3171 static const uint16_t GPR_32[] = { // 32-bit registers.
3175 static const uint16_t GPR_64[] = { // 64-bit registers.
3179 static const uint16_t *FPR = GetFPR();
3181 static const uint16_t VR[] = {
3185 const unsigned NumGPRs = array_lengthof(GPR_32);
3186 const unsigned NumFPRs = 13;
3187 const unsigned NumVRs = array_lengthof(VR);
3189 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
3230 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
3231 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3258 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3259 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3471 const SmallVectorImpl<ISD::OutputArg> &Outs,
3472 LLVMContext &Context) const {
3482 const SmallVectorImpl<ISD::OutputArg> &Outs,
3483 const SmallVectorImpl<SDValue> &OutVals,
3484 DebugLoc dl, SelectionDAG &DAG) const {
3516 const PPCSubtarget &Subtarget) const {
3548 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3572 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3599 const PPCSubtarget &Subtarget) const {
3620 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3694 DebugLoc dl) const {
3730 SelectionDAG &DAG) const {
3780 SelectionDAG &DAG) const {
3843 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3872 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3901 const {
3940 static const EVT VTys[] = { // canonical VT to use for each size.
4003 SelectionDAG &DAG) const {
4067 static const signed char SplatCsts[] = {
4084 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4095 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4106 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4118 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4245 SelectionDAG &DAG) const {
4410 SelectionDAG &DAG) const {
4478 SelectionDAG &DAG) const {
4495 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
4556 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4604 SelectionDAG &DAG) const {
4605 const TargetMachine &TM = getTargetMachine();
4699 bool is64bit, unsigned BinOpcode) const {
4701 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4703 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4726 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4727 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4762 unsigned BinOpcode) const {
4764 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4772 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4793 const TargetRegisterClass *RC =
4794 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4795 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4891 MachineBasicBlock *BB) const {
4892 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4896 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5115 const TargetRegisterClass *RC =
5116 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5117 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5249 DAGCombinerInfo &DCI) const {
5250 const TargetMachine &TM = getTargetMachine();
5509 void PPCTargetLowering::computeMaskedBitsForTargetNode(const
5512 const SelectionDAG &DAG,
5513 unsigned Depth) const {
5550 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5570 AsmOperandInfo &info, const char *constraint) const {
5606 std::pair<unsigned, const TargetRegisterClass*>
5607 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5608 EVT VT) const {
5639 SelectionDAG &DAG) const {
5706 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5707 Type *Ty) const {
5743 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{
5748 bool PPCTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const {
5753 SelectionDAG &DAG) const {
5787 SelectionDAG &DAG) const {
5813 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5834 MachineFunction &MF) const {
5842 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
