Lines Matching defs:BaseReg
165 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
168 if ((BaseReg.getReg() != 0 &&
169 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
180 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
183 if ((BaseReg.getReg() != 0 &&
184 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
195 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
198 if ((BaseReg.getReg() != 0 &&
199 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
305 unsigned BaseReg = Base.getReg();
308 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
333 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
336 // If no BaseReg, issue a RIP relative instruction only if the MCE can
348 (!is64BitMode() || BaseReg != 0)) {
350 if (BaseReg == 0) { // [disp32] in X86-32 mode
385 if (BaseReg == 0) {
413 if (BaseReg == 0) {
