Lines Matching defs:Sub
358 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
472 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
712 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
848 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
849 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
850 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
851 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
1080 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1081 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1082 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1083 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1105 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1106 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1107 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1188 // Add/Sub/Mul with overflow operations are custom lowered.
1222 setTargetDAGCombine(ISD::SUB);
7641 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7646 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7648 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7653 Sub);
7692 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7698 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7701 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7705 return Sub;
8163 case ISD::SUB:
8176 case ISD::SUB: Opcode = X86ISD::SUB; break;
8185 case X86ISD::SUB:
8518 Opc == X86ISD::SUB ||
8634 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8635 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8739 // Check for setcc([su]{add,sub,mul}o == 0).
8761 Cond.getOpcode() == X86ISD::SUB ||
8814 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8815 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9965 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
10311 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10354 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10469 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10506 BaseOp = X86ISD::SUB;
10510 BaseOp = X86ISD::SUB;
10757 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10809 case ISD::SUBC: Opc = X86ISD::SUB; break;
10892 case ISD::SUB: return LowerSUB(Op, DAG);
11148 case X86ISD::SUB: return "X86ISD::SUB";
12795 case X86ISD::SUB:
14069 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14074 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14183 // psign = x.type == y.type == mask.type && y = sub(0, x);
14184 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14232 if (ShAmt0.getOpcode() == ISD::SUB) {
14239 if (ShAmt1.getOpcode() == ISD::SUB) {
14634 "Unsupported vector type for horizontal add/sub");
14636 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14992 // (sub (sete X, 0), Y) -> sbb 0, Y
14993 // (sub (setne X, 0), Y) -> adc -1, Y
14998 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15020 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15022 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15025 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15051 // X86 can't encode an immediate LHS of a sub. See if we can push the
15054 // If the RHS of the sub is a XOR with one use and a constant, invert the
15055 // immediate. Then add one to the LHS of the sub so we can turn
15090 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15151 case ISD::SUB:
15211 case ISD::SUB: {
15610 } else if (Op.getOpcode() == ISD::SUB) {
