Lines Matching defs:Upper
3206 // Upper quadword shuffled.
3220 // Upper quadword copied in order.
4033 /// match movhlps. The lower half elements should come from upper half of
4034 /// V1 (and in order), and the upper half elements should come from the upper
4089 /// V1 (and in order), and the upperupper
5210 // Build both the lower and upper subvector.
5212 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5215 // Recreate the wider vector with the lower and upper part.
5218 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
6780 bool Upper = IdxVal >= NumElems/2;
6782 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6785 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6920 bool Upper = IdxVal >= NumElems/2;
6921 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6926 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6985 // upper bits of a vector.
7003 // the upper bits of a vector.
7672 // Zero out the upper parts of the register.
9758 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
14895 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14896 // Concat upper and lower parts.
14900 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14901 // Concat upper and lower parts.
