Lines Matching refs:Index
63 /// simple subregister reference. Idx is an index in the 128 bits we
88 // This is the index of the first element of the 128-bit chunk
105 /// simple superregister reference. Idx is an index in the 128 bits
124 // This is the index of the first element of the 128-bit chunk
975 // the index is constant. For now custom expand to deal with that.
1926 // If the function takes variable number of arguments, make a frame index for
2373 // Create frame index.
3830 // The index should be aligned on a 128-bit boundary.
3831 uint64_t Index =
3837 bool Result = (Index * ElSize) % 128 == 0;
3849 // The index should be aligned on a 128-bit boundary.
3850 uint64_t Index =
3856 bool Result = (Index * ElSize) % 128 == 0;
3948 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3954 uint64_t Index =
3961 return Index / NumElemsPerChunk;
3965 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3971 uint64_t Index =
3978 return Index / NumElemsPerChunk;
4330 // the splat element index when it refers to the higher register.
4422 // The index 0 always comes from the first element of the second source,
4453 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4464 int Elt = SV->getMaskElt(Index);
4485 int Elt = ShuffleMask[Index];
4506 return (Index == 0) ? V.getOperand(0)
4510 return V.getOperand(Index);
4523 unsigned Index
4524 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4535 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4583 0, // Mask Start Index
4584 NumElems-NumZeros, // Mask End Index(exclusive)
4616 NumZeros, // Mask Start Index
4617 NumElems, // Mask End Index(exclusive)
5999 // the mask element does not index into any input vector.
6007 // Turn the index into an offset from the start of the input vector.
6028 // Add the mask index for the new shuffle vector.
6080 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6737 // the case of a store, it's not worth it if the index is a constant 0,
6754 // ExtractPS/pextrq works with constant index.
6882 // zero here. The DAG Combiner may combine an extract_elt index into these
6895 // PINSR* works with constant index.
7392 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
10609 DAG.getRegister(0, MVT::i32), // Index
10665 DAG.getRegister(0, MVT::i32), // Index
11391 // x86 address has 4 operands: base, index, scale, and displacement
11510 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11662 // x86 address has 4 operands: base, index, scale, and displacement
11817 MachineOperand &Index = MI->getOperand(3);
11924 .addOperand(Index)
11949 .addOperand(Index)
11976 .addOperand(Index)
11996 .addOperand(Index)
12032 .addOperand(Index)
13187 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
14715 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14716 if (!(LIdx == Index && RIdx == Index + 1) &&
14717 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14787 // BT ignores high bits in the bit index operand.
