Lines Matching refs:v4i32
840 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
845 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
850 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
863 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
875 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
906 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
935 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
936 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
952 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
957 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
994 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
997 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
999 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1002 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1005 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1007 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1338 return MVT::v4i32;
1422 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
3189 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
4170 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4208 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4215 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5028 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5035 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5038 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5090 EVT VecVT = MVT::v4i32;
5137 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5354 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5438 case MVT::v4i32:
5893 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5909 case MVT::v4i32: NewVT = MVT::v2i64; break;
5910 case MVT::v8i16: NewVT = MVT::v4i32; break;
5911 case MVT::v16i8: NewVT = MVT::v4i32; break;
5956 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6252 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6265 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6271 // v4i32 or v4f32
6325 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6368 } else if ((VT == MVT::v4i32 ||
6473 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6500 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6725 MVT::v4i32,
6749 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6806 MVT::v4i32, Vec),
6980 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7630 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7633 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7634 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7648 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7649 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7669 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
9229 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10225 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10259 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10362 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10588 case MVT::v4i32:
13034 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13042 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13043 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13060 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13063 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13080 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13081 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13086 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13200 if (InputVector.getValueType() != MVT::v4i32)
13825 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13902 case MVT::v4i32:
13912 case MVT::v4i32:
13922 case MVT::v4i32:
14827 // v4i32 to v4i64
14830 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14831 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14839 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14894 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14895 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14898 // v4i32 -> v4i64
14899 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14900 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14906 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
15038 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15071 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15723 case MVT::v4i32:
