Lines Matching refs:prefetch
90 0x40 prefetch_hit Counts L2 prefetch hits for both code and data
91 0x80 prefetch_miss Counts L2 prefetch misses for both code and data
101 0x10 i_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the I (invalid) state, i
102 0x20 s_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the S (shared) state
103 0x40 e_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the E (exclusive) state
104 0x80 m_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the M (modified) state
105 0xF0 mesi Counts all L2 prefetch requests
162 0x01 nta Counts number of SSE NTA prefetch/weakly-ordered instructions which missed the L1 data cache
165 0x01 requests Counts number of hardware prefetch requests dispatched out of the prefetch FIFO
166 0x02 miss Counts number of hardware prefetch requests that miss the L1D
167 0x04 triggers Counts number of prefetch requests triggered by the Finite State Machine and pushed into the prefetch FIFO
328 0x01 load Counts L2 load operations due to HW prefetch or demand loads
329 0x02 rfo Counts L2 RFO operations due to HW prefetch or demand RFOs
330 0x04 ifetch Counts L2 instruction fetch operations due to HW prefetch or demand ifetch
331 0x08 prefetch Counts L2 prefetch operations
333 0x20 fill Counts L2 cache line fill operations due to load, RFO, L1D writeback or prefetch
343 0x04 prefetch_clean Counts L2 clean cache line evicted by a prefetch request
344 0x08 prefetch_dirty Counts L2 modified cache line evicted by a prefetch request
