Lines Matching refs:misses
64 0x01 any DTLB load misses
71 0x01 any DTLB misses
74 0x10 stlb_hit DTLB first level misses but second level hit
75 0x20 pde_miss DTLB misses casued by low part of address
116 0x02 miss L1D hardware prefetch misses
119 0x01 i_state L1 writebacks to L2 in I state (misses)
126 0x02 misses L1I instruction fetch misses
130 0x01 demand_i_state L2 data demand loads in I state (misses)
135 0x10 prefetch_i_state L2 data prefetches in the I state (misses)
153 0x02 ld_miss L2 load misses
156 0x08 rfo_miss L2 RFO misses
159 0x20 ifetch_miss L2 instruction fetch misses
162 0x80 prefetch_miss L2 prefetch misses
163 0xaa miss All L2 misses
176 0x01 rfo_i_state L2 demand store RFOs in I state (misses)
181 0x10 lock_i_state L2 demand lock RFOs in I state (misses)
