Lines Matching refs:op
30 #include "tcg-op.h"
2484 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2488 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2493 if ((cpm == 5 && op == 4)
2494 || (cpm == 10 && (op == 4 || op == 5)))
2505 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2514 switch (op) {
2531 switch (op) {
2565 /* mcrr. Used for block cache operations, so implement as no-op. */
2727 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2944 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2946 if (op == 15) {
2954 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
2960 if (op == 15 &&
2971 if (op == 15 && rn == 15) {
2984 if (op == 15 && rn > 3)
3019 if (op == 15) {
3062 switch (op) {
3133 /* no-op */
3268 printf ("op:%d\n", op);
3273 if (op == 15 && (rn >= 8 && rn <= 11))
3275 else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
3278 else if (op == 15 && rn == 15)
3288 if (op == 15 && delta_m == 0) {
3302 if (op == 15) {
3830 int op;
3852 op = (insn >> 8) & 0xf;
3854 if (op > 10)
3857 switch (op & 0xc) {
3871 nregs = neon_ls_element_type[op].nregs;
3872 interleave = neon_ls_element_type[op].interleave;
3873 spacing = neon_ls_element_type[op].spacing;
4219 static void gen_neon_narrow_op(int op, int u, int size, TCGv dest, TCGv_i64 src)
4221 if (op) {
4236 /* Symbolic constants for op fields for Neon 3-register same-length.
4275 [NEON_3R_LOGIC] = 0xf, /* size field encodes op type */
4296 [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */
4297 [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */
4298 [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */
4299 [NEON_3R_FLOAT_ACMP] = 0x5, /* size bit 1 encodes op */
4300 [NEON_3R_FLOAT_MINMAX] = 0x5, /* size bit 1 encodes op */
4301 [NEON_3R_VRECPS_VRSQRTS] = 0x5, /* size bit 1 encodes op */
4304 /* Symbolic constants for op fields for Neon 2-register miscellaneous.
4353 static int neon_2rm_is_float_op(int op)
4355 /* Return true if this neon 2reg-misc op is float-to-float */
4356 return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F ||
4357 op >= NEON_2RM_VRECPE_F);
4362 * op values will have no bits set they always UNDEF.
4418 int op;
4441 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
4442 /* Catch invalid op and bad size combinations: UNDEF */
4443 if ((neon_3r_sizes[op] & (1 << size)) == 0) {
4452 if (size == 3 && op != NEON_3R_LOGIC) {
4457 switch (op) {
4515 switch (op) {
4590 switch (op) {
4841 op = (insn >> 8) & 0xf;
4844 if (op > 7) {
4856 if (op < 8) {
4862 if (!u && (op == 4 || op == 6)) {
4867 if (op <= 4)
4896 switch (op) {
4928 if (op == 1 || op == 3) {
4932 } else if (op == 4 || (op == 5 && u)) {
4939 if (op == 4) {
4953 switch (op) {
4992 if (op == 1 || op == 3) {
4997 } else if (op == 4 || (op == 5 && u)) {
5001 if (op == 4)
5009 if (op == 4)
5019 if (op == 4)
5037 } else if (op < 10) {
5040 int input_unsigned = (op == 8) ? !u : u;
5071 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
5105 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
5110 } else if (op == 10) {
5153 } else if (op >= 14) {
5164 if (!(op & 1)) {
5186 op = (insn >> 8) & 0xf;
5190 /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
5194 switch (op) {
5196 /* no-op */
5236 if (op & 1 && op < 12) {
5248 if (op == 14 && invert) {
5266 op = (insn >> 8) & 0xf;
5298 prewiden = neon_3reg_wide[op][0];
5299 src1_wide = neon_3reg_wide[op][1];
5300 src2_wide = neon_3reg_wide[op][2];
5301 undefreq = neon_3reg_wide[op][3];
5352 switch (op) {
5396 if (op == 13) {
5400 } else if (op == 5 || (op >= 8 && op <= 11)) {
5403 switch (op) {
5412 if (op == 11) {
5421 } else if (op == 4 || op == 6) {
5473 switch (op) {
5494 if (op == 12) {
5500 } else if (op == 13) {
5506 } else if (op & 1) {
5517 if (op < 8) {
5520 switch (op) {
5569 if (op != 11) {
5572 switch (op) {
5581 if (op == 7) {
5587 /* no-op */
5662 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5664 /* UNDEF for unknown op values and bad op-size combinations */
5665 if ((neon_2rm_sizes[op] & (1 << size)) == 0) {
5668 if ((op != NEON_2RM_VMOVN && op != NEON_2RM_VQMOVN) &&
5672 switch (op) {
5680 case 2: /* no-op */ break;
5700 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5702 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5709 if (op >= NEON_2RM_VPADAL) {
5741 /* also VQMOVUN; op field and mnemonics don't line up */
5749 gen_neon_narrow_op(op == NEON_2RM_VMOVN, q, size,
5824 if (neon_2rm_is_float_op(op)) {
5831 switch (op) {
5889 if (op == NEON_2RM_VCLE0) {
5902 if (op == NEON_2RM_VCLT0) {
5998 /* Reserved op values were caught by the
6003 if (neon_2rm_is_float_op(op)) {
6507 /* We don't emulate caches so these are a no-op. */
7696 /* Return true if this is a Thumb-2 logical op. */
7698 thumb2_logic_op(int op)
7700 return (op < 8);
7710 gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1)
7715 switch (op) {
7788 int op;
7931 op = (insn >> 4) & 0x3;
7932 if (op == 2) {
7938 gen_load_exclusive(s, rs, rd, addr, op);
7940 gen_store_exclusive(s, rm, rs, rd, addr, op);
7973 op = (insn & 0x1f);
7975 tmp = tcg_const_i32(op);
7993 tmp = tcg_const_i32(op);
8058 op = (insn >> 21) & 0xf;
8059 if (op == 6) {
8094 logic_cc = (conds && thumb2_logic_op(op));
8096 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
8107 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
8108 if (op < 4 && (insn & 0xf000) != 0xf000)
8110 switch (op) {
8116 op = (insn >> 21) & 3;
8118 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
8130 op = (insn >> 20) & 7;
8131 switch (op) {
8142 if ((op >> 1) == 1) {
8152 op = (insn >> 20) & 7;
8154 if ((op & 3) == 3 || (shift & 3) == 3)
8158 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
8163 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
8164 if (op < 4) {
8168 if (op & 1)
8170 if (op & 2)
8177 switch (op) {
8208 op = (insn >> 4) & 0xf;
8217 if (op)
8225 gen_mulxy(tmp, tmp2, op & 2, op & 1);
8235 if (op)
8257 if (op)
8304 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
8307 if ((op & 0x50) == 0x10) {
8311 if (op & 0x20)
8317 } else if ((op & 0xe) == 0xc) {
8319 if (op & 1)
8322 if (op & 0x10) {
8336 if (op & 0x20) {
8340 if (op & 8) {
8342 gen_mulxy(tmp, tmp2, op & 2, op & 1);
8352 if (op & 4) {
8356 } else if (op & 0x40) {
8422 op = (insn >> 20) & 7;
8423 switch (op) {
8440 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
8441 op == 1, tmp))
8473 op = (insn >> 4) & 0xf;
8474 switch (op) {
8525 op = (insn >> 22) & 0xf;
8528 gen_test_cc(op ^ 1, s->condlabel);
8552 op = (insn >> 21) & 7;
8561 switch (op) {
8590 if (op & 1)
8596 if (op & 4) {
8598 if ((op & 1) && shift == 0)
8604 if ((op & 1) && shift == 0)
8685 op = (insn >> 21) & 0xf;
8686 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
8709 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8714 if (op != 2) {
8728 if (op & 2) {
8806 switch (op) {
8824 switch (op) {
8852 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8880 op = (insn >> 11) & 3;
8881 if (op == 3) {
8912 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
8920 op = (insn >> 11) & 3;
8922 if (op == 0) { /* mov */
8932 switch (op) {
8974 op = (insn >> 8) & 3;
8975 switch (op) {
9013 op = (insn >> 6) & 0xf;
9014 if (op == 2 || op == 3 || op == 4 || op == 7) {
9024 if (op == 9) { /* neg */
9027 } else if (op != 0xf) { /* mvn doesn't read its first operand */
9034 switch (op) {
9135 if (op != 0xf)
9152 op = (insn >> 9) & 7;
9158 if (op < 3) /* store */
9161 switch (op) {
9187 if (op >= 3) /* load */
9289 op = (insn >> 8) & 0xf;
9290 switch (op) {
