Lines Matching full:rounding
49 * FP rounding mode observed only for float->int conversions and
51 float-to-float rounding. For all other operations,
4591 /* --------- Get/put the FPU rounding mode. --------- */
4604 /* --------- Synthesise a 2-bit FPU rounding mode. --------- */
5122 rounding mode. Therefore, pass the 16-bit value
8638 /* Get the current SSE rounding mode. */
9593 I32 in mmx, according to prevailing SSE rounding mode */
9595 I32 in mmx, rounding towards zero */
9650 according to prevailing SSE rounding mode
9652 according to prevailing SSE rounding mode
9732 /* The only thing we observe in %mxcsr is the rounding mode.
10096 /* 0F E0 = PAVGB -- 8x8 unsigned Packed Average, with rounding */
10106 /* 0F E3 = PAVGW -- 16x4 unsigned Packed Average, with rounding */
10713 lo half xmm(G), and zero upper half, rounding towards zero */
10715 lo half xmm(G), according to prevailing rounding mode, and zero
10769 I32 in mmx, according to prevailing SSE rounding mode */
10771 I32 in mmx, rounding towards zero */
10821 lo half xmm(G), rounding according to prevailing SSE rounding
10908 xmm(G), rounding towards zero */
10910 xmm(G), as per the prevailing rounding mode */
10993 according to prevailing SSE rounding mode
10995 according to prevailing SSE rounding mode
11045 low 1/4 xmm(G), according to prevailing SSE rounding mode */
15489 /* (imm & 3) contains an Intel-encoded rounding mode. Because
15491 we can use that value directly in the IR as a rounding
15546 /* (imm & 3) contains an Intel-encoded rounding mode. Because
15548 we can use that value directly in the IR as a rounding
15613 /* (imm & 3) contains an Intel-encoded rounding mode. Because
15615 we can use that value directly in the IR as a rounding
