Lines Matching full:rounding
2467 /* We're only keeping track of the rounding mode,
2592 /* Allow writes to Rounding Mode */
6666 /* --------- Synthesise a 2-bit FPU rounding mode. --------- */
6674 rounding mode | PPC | IR
6722 /* These are completely straightforward from a rounding and status
6723 bits perspective: no rounding involved and no funny status or CR
6872 rounding. */
7237 /* Bind the rounding mode expression to a temp; there's no
7247 /* The rounding in this is all a bit dodgy. The idea is to only do
7248 one rounding. That clearly isn't achieveable without dedicated
7253 In the negated cases, the negation happens after rounding. */
7837 Floating Point Rounding/Conversion Instructions
8333 * the rounding mode. The HW exception bits do not get set in
10112 case 0x1D6: // xvrdpic (VSX Vector Round to Double-Precision Integer using Current rounding mode)
10136 case 0x156: // xvrspic (VSX Vector Round to SinglePrecision Integer using Current rounding mode)
10722 case 0x0D6: // xsrdpic (VSX Scalar Round to Double-Precision Integer using Current rounding mode)
13760 /* Floating Point Rounding/Conversion Instructions */
13775 /* Power6 rounding stuff */
