Lines Matching full:rounding
52 * FP rounding mode observed only for float->int conversions
54 for float-to-float rounding. For all other operations,
3463 /* --------- Get/put the FPU rounding mode. --------- */
3475 /* --------- Synthesise a 2-bit FPU rounding mode. --------- */
3971 rounding mode. Therefore, pass the 16-bit value
7350 /* Get the current SSE rounding mode. */
8394 I32 in mmx, according to prevailing SSE rounding mode */
8396 I32 in mmx, rounding towards zero */
8449 I32 in ireg, according to prevailing SSE rounding mode */
8451 I32 in ireg, rounding towards zero */
8518 /* The only thing we observe in %mxcsr is the rounding mode.
8842 /* 0F E0 = PAVGB -- 8x8 unsigned Packed Average, with rounding */
8851 /* 0F E3 = PAVGW -- 16x4 unsigned Packed Average, with rounding */
9490 I32 in mmx, according to prevailing SSE rounding mode */
9492 I32 in mmx, rounding towards zero */
9697 I32 in ireg, according to prevailing SSE rounding mode */
9699 I32 in ireg, rounding towards zero */
9736 low 1/4 xmm(G), according to prevailing SSE rounding mode */
9819 lo half xmm(G), and zero upper half, rounding towards zero */
9862 xmm(G), rounding towards zero */
12608 the rounding mode is specified directly by the immediate byte.)
12644 /* (imm & 3) contains an Intel-encoded rounding mode. Because
12646 we can use that value directly in the IR as a rounding
