Lines Matching full:pipeline
5941 that otherwise would cause pipeline stalls. This pass is
21508 `dbra'-like instruction and avoids pipeline stalls associated with the
21883 output is not available for multiple cycles (*note Processor pipeline
22429 * Processor pipeline description:: Specifying information for insn scheduling.
22906 File: gccint.info, Node: Delay Slots, Next: Processor pipeline description, Prev: Constant Attributes, Up: Insn Attributes
22975 File: gccint.info, Node: Processor pipeline description, Prev: Delay Slots, Up: Insn Attributes
22977 16.19.8 Specifying processor pipeline description
22985 Such "interlock (pipeline) delay" causes interruption of the fetching
23008 processor parallelism (or "pipeline description"). GCC machine
23013 The GCC instruction scheduler uses a "pipeline hazard recognizer" to
23015 a given simulated processor cycle. The pipeline hazard recognizer is
23016 automatically generated from the processor pipeline description. The
23017 pipeline hazard recognizer generated from the machine description is
23024 automaton-based processor pipeline description. The order of these
23028 generated and used for the pipeline hazards recognition. Sometimes the
23029 generated finite state automaton used by the pipeline hazard recognizer
23080 The following construction is the major one to describe pipeline
23088 automaton based pipeline description. The latency time is used for all
23090 pipeline description, the given latency time is only used for true
23108 defined. Such cases are not checked during generation of the pipeline
23111 contain `symbol_ref'). It is also not checked during the pipeline
23161 In such case, you can simplify the pipeline description by describing
23270 You can control the generator of the pipeline hazard recognizer with
23305 generated states, you could interrupt the generator of the pipeline
23317 All simple integer insns can be executed in any integer pipeline and
23319 issued into the first pipeline unless it is reserved, otherwise they
23320 are issued into the second pipeline. Integer division and
23322 pipeline and their results are ready correspondingly in 8 and 4 cycles.
29467 using the traditional pipeline description that an output- or
29469 If the scheduler using the automaton based pipeline description,
29474 *note Processor pipeline description::.
29559 pipeline hazard recognizer is changed as if the insn were scheduled
29561 may simplify the automaton pipeline description for some VLIW
29563 automaton based pipeline description. The default is not to
29609 pipeline B. The processor may issue the 1st insn into A and the
29615 pipeline hazard recognizer. We try quickly and easy many insn
40623 * absence_set: Processor pipeline description.
40789 * automata_option: Processor pipeline description.
40791 * automaton based pipeline description: Processor pipeline description.
40793 * automaton based scheduler: Processor pipeline description.
41152 * data bypass: Processor pipeline description.
41154 * data dependence delays: Processor pipeline description.
41265 * define_automaton: Processor pipeline description.
41267 * define_bypass: Processor pipeline description.
41276 * define_cpu_unit: Processor pipeline description.
41284 * define_insn_reservation: Processor pipeline description.
41294 * define_query_cpu_unit: Processor pipeline description.
41297 * define_reservation: Processor pipeline description.
41322 * deterministic finite state automaton: Processor pipeline description.
41433 * exclusion_set: Processor pipeline description.
41470 * final_absence_set: Processor pipeline description.
41473 * final_presence_set: Processor pipeline description.
41480 * finite state automaton minimization: Processor pipeline description.
42187 * instruction latency time: Processor pipeline description.
42200 * interlock delays: Processor pipeline description.
42567 * nondeterministic finite state automaton: Processor pipeline description.
42711 * pipeline hazard recognizer: Processor pipeline description.
42760 * presence_set: Processor pipeline description.
42770 * processor functional units: Processor pipeline description.
42772 * processor pipeline description: Processor pipeline description.
42814 * querying function unit reservations: Processor pipeline description.
42942 * regular expressions: Processor pipeline description.
42955 * reservation delays: Processor pipeline description.
42990 * RISC: Processor pipeline description.
43924 * VLIW: Processor pipeline description.
44206 Node: Processor pipeline description986110
44207 Ref: Processor pipeline description-Footnote-11003476
