Lines Matching full:pipeline
5940 that otherwise would cause pipeline stalls. This pass is
21507 `dbra'-like instruction and avoids pipeline stalls associated with the
21882 output is not available for multiple cycles (*note Processor pipeline
22428 * Processor pipeline description:: Specifying information for insn scheduling.
22905 File: gccint.info, Node: Delay Slots, Next: Processor pipeline description, Prev: Constant Attributes, Up: Insn Attributes
22974 File: gccint.info, Node: Processor pipeline description, Prev: Delay Slots, Up: Insn Attributes
22976 16.19.8 Specifying processor pipeline description
22984 Such "interlock (pipeline) delay" causes interruption of the fetching
23007 processor parallelism (or "pipeline description"). GCC machine
23012 The GCC instruction scheduler uses a "pipeline hazard recognizer" to
23014 a given simulated processor cycle. The pipeline hazard recognizer is
23015 automatically generated from the processor pipeline description. The
23016 pipeline hazard recognizer generated from the machine description is
23023 automaton-based processor pipeline description. The order of these
23027 generated and used for the pipeline hazards recognition. Sometimes the
23028 generated finite state automaton used by the pipeline hazard recognizer
23079 The following construction is the major one to describe pipeline
23087 automaton based pipeline description. The latency time is used for all
23089 pipeline description, the given latency time is only used for true
23107 defined. Such cases are not checked during generation of the pipeline
23110 contain `symbol_ref'). It is also not checked during the pipeline
23160 In such case, you can simplify the pipeline description by describing
23269 You can control the generator of the pipeline hazard recognizer with
23304 generated states, you could interrupt the generator of the pipeline
23316 All simple integer insns can be executed in any integer pipeline and
23318 issued into the first pipeline unless it is reserved, otherwise they
23319 are issued into the second pipeline. Integer division and
23321 pipeline and their results are ready correspondingly in 8 and 4 cycles.
29465 using the traditional pipeline description that an output- or
29467 If the scheduler using the automaton based pipeline description,
29472 *note Processor pipeline description::.
29557 pipeline hazard recognizer is changed as if the insn were scheduled
29559 may simplify the automaton pipeline description for some VLIW
29561 automaton based pipeline description. The default is not to
29607 pipeline B. The processor may issue the 1st insn into A and the
29613 pipeline hazard recognizer. We try quickly and easy many insn
40617 * absence_set: Processor pipeline description.
40783 * automata_option: Processor pipeline description.
40785 * automaton based pipeline description: Processor pipeline description.
40787 * automaton based scheduler: Processor pipeline description.
41144 * data bypass: Processor pipeline description.
41146 * data dependence delays: Processor pipeline description.
41256 * define_automaton: Processor pipeline description.
41258 * define_bypass: Processor pipeline description.
41267 * define_cpu_unit: Processor pipeline description.
41275 * define_insn_reservation: Processor pipeline description.
41285 * define_query_cpu_unit: Processor pipeline description.
41288 * define_reservation: Processor pipeline description.
41313 * deterministic finite state automaton: Processor pipeline description.
41424 * exclusion_set: Processor pipeline description.
41461 * final_absence_set: Processor pipeline description.
41464 * final_presence_set: Processor pipeline description.
41471 * finite state automaton minimization: Processor pipeline description.
42178 * instruction latency time: Processor pipeline description.
42191 * interlock delays: Processor pipeline description.
42558 * nondeterministic finite state automaton: Processor pipeline description.
42702 * pipeline hazard recognizer: Processor pipeline description.
42751 * presence_set: Processor pipeline description.
42761 * processor functional units: Processor pipeline description.
42763 * processor pipeline description: Processor pipeline description.
42805 * querying function unit reservations: Processor pipeline description.
42933 * regular expressions: Processor pipeline description.
42946 * reservation delays: Processor pipeline description.
42981 * RISC: Processor pipeline description.
43914 * VLIW: Processor pipeline description.
44196 Node: Processor pipeline description986109
44197 Ref: Processor pipeline description-Footnote-11003475
